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dts: add 850M clk configure

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PD#156734: dts: add 850M clk configure

the signoff maxfreq is 850M using gp0_pll.
this may conflict with dsi pannel. donot configure 850M if dsi was used.

Change-Id: I1a861163d97740404f9977993394d0ccb7ce929d
Signed-off-by: Jiyu Yang <Jiyu.Yang@amlogic.com>
This commit is contained in:
Jiyu Yang
2018-02-08 11:10:05 +08:00
committed by Yixun Lan
parent 39ca1ac1e8
commit ca9cf38b2f
1 changed files with 9 additions and 9 deletions
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18
arch/arm64/boot/dts/amlogic/mesong12a-dvalin.dtsi
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@@ -93,21 +93,21 @@
threshold = <210 236>;
};
dvfs750_cfg:dvfs750_cfg {
clk_freq = <744000000>;
clk_parent = "gp0_pll";
clkp_freq = <744000000>;
clk_reg = <0x200>;
dvfs800_cfg:dvfs800_cfg {
clk_freq = <800000000>;
clk_parent = "fclk_div2p5";
clkp_freq = <800000000>;
clk_reg = <0x600>;
voltage = <1150>;
keep_count = <5>;
threshold = <230 255>;
};
dvfs800_cfg:dvfs800_cfg {
clk_freq = <800000000>;
dvfs850_cfg:dvfs850_cfg {
clk_freq = <846000000>;
clk_parent = "gp0_pll";
clkp_freq = <800000000>;
clk_reg = <0x600>;
clkp_freq = <846000000>;
clk_reg = <0x200>;
voltage = <1150>;
keep_count = <5>;
threshold = <230 255>;