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media: i2c: techpoint: fix tp9951 2 lane ecc error
Signed-off-by: LongChang Ma <chad.ma@rock-chips.com> Change-Id: Iddc95c2a0512e25d8a8c9575a5a55161c5c47b6d
This commit is contained in:
LongChang Ma
@@ -15,9 +15,9 @@ static struct techpoint_video_modes supported_modes[] = {
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.width = 960,
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.height = 576,
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.max_fps = {
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.numerator = 10000,
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.denominator = 250000,
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},
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.numerator = 10000,
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.denominator = 250000,
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},
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.link_freq_value = TP9951_LINK_FREQ_148M,
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.common_reg_list = NULL,
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.common_reg_size = 0,
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@@ -35,9 +35,9 @@ static struct techpoint_video_modes supported_modes[] = {
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.width = 960,
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.height = 480,
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.max_fps = {
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.numerator = 10000,
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.denominator = 250000,
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},
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.numerator = 10000,
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.denominator = 250000,
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},
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.link_freq_value = TP9951_LINK_FREQ_148M,
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.common_reg_list = NULL,
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.common_reg_size = 0,
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@@ -55,11 +55,11 @@ static struct techpoint_video_modes supported_modes[] = {
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.width = 1920,
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.height = 1080,
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.max_fps = {
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.numerator = 10000,
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.denominator = 250000,
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},
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// .link_freq_value = TP9951_LINK_FREQ_594M,
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.link_freq_value = TP9951_LINK_FREQ_297M,
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.numerator = 10000,
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.denominator = 250000,
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},
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.link_freq_value = TP9951_LINK_FREQ_594M,
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//.link_freq_value = TP9951_LINK_FREQ_297M,
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.common_reg_list = NULL,
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.common_reg_size = 0,
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.bpp = TP9951_BITS_PER_SAMPLE,
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@@ -76,9 +76,9 @@ static struct techpoint_video_modes supported_modes[] = {
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.width = 1280,
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.height = 720,
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.max_fps = {
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.numerator = 10000,
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.denominator = 250000,
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},
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.numerator = 10000,
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.denominator = 250000,
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},
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.link_freq_value = TP9951_LINK_FREQ_297M,
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.common_reg_list = NULL,
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.common_reg_size = 0,
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@@ -136,12 +136,12 @@ int tp9951_get_all_input_status(struct techpoint *techpoint, u8 *detect_status)
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}
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static void tp9951_set_mipi_out(struct i2c_client *client,
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enum techpoint_support_reso reso,
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unsigned char lane)
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enum techpoint_support_reso reso,
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unsigned char lane)
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{
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u8 tmp;
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//mipi setting
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techpoint_write_reg(client, 0x40, 0x08); //select MIPI page
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techpoint_write_reg(client, PAGE_REG, 0x08); //select MIPI page
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techpoint_write_reg(client, 0x02, 0x7d);
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techpoint_write_reg(client, 0x03, 0x75);
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techpoint_write_reg(client, 0x04, 0x75);
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@@ -213,11 +213,11 @@ static void tp9951_set_mipi_out(struct i2c_client *client,
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}
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}
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techpoint_write_reg(client, 0x40, 0x00); //back to decoder page
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techpoint_write_reg(client, PAGE_REG, 0x00); //back to decoder page
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techpoint_read_reg(client, 0x06, &tmp); //PLL reset
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techpoint_write_reg(client, 0x06, 0x80 | tmp);
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techpoint_write_reg(client, 0x40, 0x08); //back to mipi page
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techpoint_write_reg(client, PAGE_REG, 0x08); //back to mipi page
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techpoint_read_reg(client, 0x14, &tmp); //PLL reset
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techpoint_write_reg(client, 0x14, 0x80 | tmp);
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@@ -226,21 +226,21 @@ static void tp9951_set_mipi_out(struct i2c_client *client,
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/* Enable MIPI CSI2 output */
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techpoint_write_reg(client, 0x28, 0x02); //stream off
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techpoint_write_reg(client, 0x28, 0x00); //stream on
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techpoint_write_reg(client, 0x40, 0x00); //back to decoder page
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techpoint_write_reg(client, PAGE_REG, 0x00); //back to decoder page
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}
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int tp9951_set_channel_reso(struct i2c_client *client, int ch,
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enum techpoint_support_reso reso)
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enum techpoint_support_reso reso)
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{
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int val = reso;
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dev_info(&client->dev, "##$$ %s", __func__);
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techpoint_write_reg(client, 0x40, 0x00); //select decoder page
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techpoint_write_reg(client, 0x06, 0x12); //default value
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techpoint_write_reg(client, 0x42, 0x00); //common setting for all format
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techpoint_write_reg(client, 0x4e, 0x00); //common setting for MIPI output
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techpoint_write_reg(client, 0x54, 0x00); //common setting for MIPI output
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techpoint_write_reg(client, 0x41, ch); //video MUX select
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techpoint_write_reg(client, 0x40, 0x00); //select decoder page
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techpoint_write_reg(client, 0x06, 0x12); //default value
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techpoint_write_reg(client, 0x42, 0x00); //common setting for all format
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techpoint_write_reg(client, 0x4e, 0x00); //common setting for MIPI output
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techpoint_write_reg(client, 0x54, 0x00); //common setting for MIPI output
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techpoint_write_reg(client, 0x41, ch); //video MUX select
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switch (val) {
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case TECHPOINT_S_RESO_720P_25:
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@@ -317,8 +317,8 @@ int tp9951_set_channel_reso(struct i2c_client *client, int ch,
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techpoint_write_reg(client, 0x18, 0x29);
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techpoint_write_reg(client, 0x19, 0x38);
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techpoint_write_reg(client, 0x1a, 0x47);
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techpoint_write_reg(client, 0x1c, 0x0a);//1920*1080, 25fps
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techpoint_write_reg(client, 0x1d, 0x50);//
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techpoint_write_reg(client, 0x1c, 0x0a); //1920*1080, 25fps
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techpoint_write_reg(client, 0x1d, 0x50);
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techpoint_write_reg(client, 0x20, 0x30);
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techpoint_write_reg(client, 0x21, 0x84);
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@@ -361,65 +361,65 @@ int tp9951_set_channel_reso(struct i2c_client *client, int ch,
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break;
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case TECHPOINT_S_RESO_1080P_30: // FHD30
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dev_err(&client->dev, "set channel PAL\n");
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techpoint_write_reg(client, 0x02, 0x40);
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techpoint_write_reg(client, 0x07, 0xc0);
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techpoint_write_reg(client, 0x0b, 0xc0);
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techpoint_write_reg(client, 0x0c, 0x03);
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techpoint_write_reg(client, 0x0d, 0x50);
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techpoint_write_reg(client, 0x02, 0x40);
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techpoint_write_reg(client, 0x07, 0xc0);
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techpoint_write_reg(client, 0x0b, 0xc0);
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techpoint_write_reg(client, 0x0c, 0x03);
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techpoint_write_reg(client, 0x0d, 0x50);
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techpoint_write_reg(client, 0x15, 0x03);
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techpoint_write_reg(client, 0x16, 0xd2);
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techpoint_write_reg(client, 0x17, 0x80);
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techpoint_write_reg(client, 0x18, 0x29);
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techpoint_write_reg(client, 0x19, 0x38);
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techpoint_write_reg(client, 0x1a, 0x47);
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techpoint_write_reg(client, 0x1c, 0x08); //1920*1080, 30fps
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techpoint_write_reg(client, 0x1d, 0x98); //
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techpoint_write_reg(client, 0x15, 0x03);
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techpoint_write_reg(client, 0x16, 0xd2);
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techpoint_write_reg(client, 0x17, 0x80);
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techpoint_write_reg(client, 0x18, 0x29);
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techpoint_write_reg(client, 0x19, 0x38);
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techpoint_write_reg(client, 0x1a, 0x47);
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techpoint_write_reg(client, 0x1c, 0x08); //1920*1080, 30fps
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techpoint_write_reg(client, 0x1d, 0x98); //
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techpoint_write_reg(client, 0x20, 0x30);
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techpoint_write_reg(client, 0x21, 0x84);
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techpoint_write_reg(client, 0x22, 0x36);
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techpoint_write_reg(client, 0x23, 0x3c);
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techpoint_write_reg(client, 0x20, 0x30);
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techpoint_write_reg(client, 0x21, 0x84);
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techpoint_write_reg(client, 0x22, 0x36);
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techpoint_write_reg(client, 0x23, 0x3c);
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techpoint_write_reg(client, 0x2b, 0x60);
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techpoint_write_reg(client, 0x2c, 0x2a);
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techpoint_write_reg(client, 0x2d, 0x30);
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techpoint_write_reg(client, 0x2e, 0x70);
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techpoint_write_reg(client, 0x2b, 0x60);
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techpoint_write_reg(client, 0x2c, 0x2a);
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techpoint_write_reg(client, 0x2d, 0x30);
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techpoint_write_reg(client, 0x2e, 0x70);
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techpoint_write_reg(client, 0x30, 0x48);
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techpoint_write_reg(client, 0x31, 0xbb);
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techpoint_write_reg(client, 0x32, 0x2e);
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techpoint_write_reg(client, 0x33, 0x90);
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techpoint_write_reg(client, 0x30, 0x48);
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techpoint_write_reg(client, 0x31, 0xbb);
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techpoint_write_reg(client, 0x32, 0x2e);
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techpoint_write_reg(client, 0x33, 0x90);
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techpoint_write_reg(client, 0x35, 0x05);
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techpoint_write_reg(client, 0x38, 0x00);
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techpoint_write_reg(client, 0x39, 0x1C);
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techpoint_write_reg(client, 0x35, 0x05);
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techpoint_write_reg(client, 0x38, 0x00);
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techpoint_write_reg(client, 0x39, 0x1C);
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if (STD_HDA) { //AHD1080p30 extra
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techpoint_write_reg(client, 0x02, 0x44);
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techpoint_write_reg(client, 0x0d, 0x72);
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if (STD_HDA) { //AHD1080p30 extra
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techpoint_write_reg(client, 0x02, 0x44);
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techpoint_write_reg(client, 0x0d, 0x72);
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techpoint_write_reg(client, 0x15, 0x01);
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techpoint_write_reg(client, 0x16, 0xf0);
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techpoint_write_reg(client, 0x18, 0x2a);
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techpoint_write_reg(client, 0x15, 0x01);
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techpoint_write_reg(client, 0x16, 0xf0);
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techpoint_write_reg(client, 0x18, 0x2a);
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techpoint_write_reg(client, 0x20, 0x38);
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techpoint_write_reg(client, 0x21, 0x46);
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techpoint_write_reg(client, 0x20, 0x38);
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techpoint_write_reg(client, 0x21, 0x46);
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techpoint_write_reg(client, 0x25, 0xfe);
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techpoint_write_reg(client, 0x26, 0x0d);
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techpoint_write_reg(client, 0x25, 0xfe);
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techpoint_write_reg(client, 0x26, 0x0d);
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techpoint_write_reg(client, 0x2c, 0x3a);
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techpoint_write_reg(client, 0x2d, 0x54);
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techpoint_write_reg(client, 0x2e, 0x40);
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techpoint_write_reg(client, 0x2c, 0x3a);
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techpoint_write_reg(client, 0x2d, 0x54);
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techpoint_write_reg(client, 0x2e, 0x40);
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techpoint_write_reg(client, 0x30, 0xa5);
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techpoint_write_reg(client, 0x31, 0x95);
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techpoint_write_reg(client, 0x32, 0xe0);
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techpoint_write_reg(client, 0x33, 0x60);
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}
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techpoint_write_reg(client, 0x30, 0xa5);
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techpoint_write_reg(client, 0x31, 0x95);
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techpoint_write_reg(client, 0x32, 0xe0);
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techpoint_write_reg(client, 0x33, 0x60);
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}
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tp9951_set_mipi_out(client, reso, MIPI_2LANE); // 2 lane
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tp9951_set_mipi_out(client, reso, MIPI_2LANE); // 2 lane
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break;
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case TECHPOINT_S_RESO_PAL:
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@@ -590,7 +590,7 @@ int tp9951_get_channel_reso(struct i2c_client *client, int ch)
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techpoint_write_reg(client, 0x40, ch);
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techpoint_read_reg(client, 0x03, &detect_fmt);
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reso = detect_fmt & 0x7;
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reso = detect_fmt & 0x7; // CVSTD[2-0]
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switch (reso) {
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case TP9951_CVSTD_720P_25:
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@@ -624,15 +624,13 @@ int tp9951_get_channel_reso(struct i2c_client *client, int ch)
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int tp9951_set_quick_stream(struct i2c_client *client, u32 stream)
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{
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// mutex_lock(&techpoint->mutex);
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if (stream) {
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techpoint_write_reg(client, 0x40, 0x8);
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techpoint_write_reg(client, 0x28, 0x0);
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techpoint_write_reg(client, PAGE_REG, 0x08);
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techpoint_write_reg(client, 0x28, 0x00);
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} else {
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techpoint_write_reg(client, 0x40, 0x8);
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techpoint_write_reg(client, 0x28, 0x2);
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techpoint_write_reg(client, PAGE_REG, 0x08);
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techpoint_write_reg(client, 0x28, 0x02);
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usleep_range(40 * 1000, 50 * 1000);
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}
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// mutex_unlock(&techpoint->mutex);
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return 0;
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}
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