mirror of
https://github.com/hardkernel/linux.git
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Merge commit '1ccd57c4b028ff3fdf84a9a50d0394bc9dffcd74'
* commit '1ccd57c4b028ff3fdf84a9a50d0394bc9dffcd74': arm64: dts: rockchip: rk3588-vehicle-s66-v10 support wifi/bt arm64: dts: rockchip: rk3588-vehicle-adsp-audio-s66 fix i2s-tdm media: rockchip: isp: fix 3dlut for multi sensor arm64: dts: rockchip: rk3528: Add trim configure for tsadc thermal: rockchip: Add trim temperature for rk3528 video: rockchip: rga3: avoid premature wake_up causing request to be freed phy: rockchip: usbdp: amend to improve USB compatibility mtd: spi-nor: xmc: Support XM25QH256C arm64: dts: rockchip: rk3588-vehicle-display-v20: not assign clock for vop media: i2c: add os02k10 driver ARM: dts: rockchip: rv1106-evb: add mcu display v20 board arm64: dts: rockchip: add rk3528 demo6 dts video: rockchip: rga3: fix memory mapping will be skipped when handle is 0 arm64: dts: rockchip: rk3568: Add opps for rk3568j/m Conflicts: arch/arm64/boot/dts/rockchip/rk3568.dtsi drivers/media/i2c/Kconfig drivers/media/i2c/Makefile drivers/mtd/spi-nor/xmc.c Ignore: commit0c5cc59876("arm64: dts: rockchip: rk3568: Add opps for rk3568j/m") commit724009a9d7("mtd: spi-nor: xmc: Support XM25QH256C") Change-Id: I07a4b82a2dfae98c894cc28af98a4e2eeb1b8006
This commit is contained in:
Tao Huang
@@ -1130,6 +1130,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
|
||||
rv1106g-38x38-ipc-v10.dtb \
|
||||
rv1106g-38x38-ipc-v10-spi-nand.dtb \
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rv1106g-evb1-mcu-display-v11.dtb \
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rv1106g-evb1-mcu-display-v20.dtb \
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rv1106g-evb1-rgb-display-v11.dtb \
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rv1106g-evb1-v10.dtb \
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rv1106g-evb1-v11.dtb \
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||||
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||||
314
arch/arm/boot/dts/rv1106g-evb1-mcu-display-v20.dts
Normal file
314
arch/arm/boot/dts/rv1106g-evb1-mcu-display-v20.dts
Normal file
@@ -0,0 +1,314 @@
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||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
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*/
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/dts-v1/;
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#include <dt-bindings/display/media-bus-format.h>
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#include "rv1106g-evb1-v11.dts"
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/ {
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model = "Rockchip RV1106G EVB1 V11 Board + RK EVB MCU 8BIT Display V20 Ext Board";
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compatible = "rockchip,rv1106g-evb1-mcu-display-v20", "rockchip,rv1106";
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backlight: backlight {
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status = "okay";
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compatible = "pwm-backlight";
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pwms = <&pwm3 0 25000 0>;
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brightness-levels = <
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0 1 2 3 4 5 6 7
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8 9 10 11 12 13 14 15
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16 17 18 19 20 21 22 23
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24 25 26 27 28 29 30 31
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||||
32 33 34 35 36 37 38 39
|
||||
40 41 42 43 44 45 46 47
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||||
48 49 50 51 52 53 54 55
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||||
56 57 58 59 60 61 62 63
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||||
64 65 66 67 68 69 70 71
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||||
72 73 74 75 76 77 78 79
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||||
80 81 82 83 84 85 86 87
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||||
88 89 90 91 92 93 94 95
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||||
96 97 98 99 100 101 102 103
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||||
104 105 106 107 108 109 110 111
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||||
112 113 114 115 116 117 118 119
|
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120 121 122 123 124 125 126 127
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||||
128 129 130 131 132 133 134 135
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||||
136 137 138 139 140 141 142 143
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||||
144 145 146 147 148 149 150 151
|
||||
152 153 154 155 156 157 158 159
|
||||
160 161 162 163 164 165 166 167
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||||
168 169 170 171 172 173 174 175
|
||||
176 177 178 179 180 181 182 183
|
||||
184 185 186 187 188 189 190 191
|
||||
192 193 194 195 196 197 198 199
|
||||
200 201 202 203 204 205 206 207
|
||||
208 209 210 211 212 213 214 215
|
||||
216 217 218 219 220 221 222 223
|
||||
224 225 226 227 228 229 230 231
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||||
232 233 234 235 236 237 238 239
|
||||
240 241 242 243 244 245 246 247
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||||
248 249 250 251 252 253 254 255>;
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default-brightness-level = <200>;
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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linux,cma {
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compatible = "shared-dma-pool";
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inactive;
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reusable;
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size = <0x1000000>;
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linux,cma-default;
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};
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drm_logo: drm-logo@00000000 {
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compatible = "rockchip,drm-logo";
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reg = <0x0 0x0>;
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};
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};
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};
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&display_subsystem {
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status = "okay";
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logo-memory-region = <&drm_logo>;
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};
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&pwm3 {
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status = "okay";
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pinctrl-names = "active";
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pinctrl-0 = <&pwm3m1_pins>;
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};
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&rgb {
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status = "okay";
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rockchip,data-sync-bypass;
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pinctrl-names = "default";
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/*
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* rgb3x8_pins for RGB3x8(8bit)
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* rgb565_pins for RGB565(16bit)
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*/
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pinctrl-0 = <&rgb3x8_pins>;
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/*
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* 320x480 RGB/MCU screen K350C4516T
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*/
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mcu_panel: mcu-panel {
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/*
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* MEDIA_BUS_FMT_RGB888_3X8 for RGB3x8(8bit)
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* MEDIA_BUS_FMT_RGB565_1X16 for RGB565(16bit)
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*/
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bus-format = <MEDIA_BUS_FMT_RGB888_3X8>;
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backlight = <&backlight>;
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enable-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
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enable-delay-ms = <20>;
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reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
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reset-delay-ms = <10>;
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prepare-delay-ms = <20>;
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unprepare-delay-ms = <20>;
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disable-delay-ms = <20>;
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init-delay-ms = <10>;
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width-mm = <217>;
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height-mm = <136>;
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// type:0 is cmd, 1 is data
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panel-init-sequence = [
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//type delay num val1 val2 val3
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00 00 01 e0
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01 00 01 00
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01 00 01 07
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01 00 01 0f
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01 00 01 0d
|
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01 00 01 1b
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01 00 01 0a
|
||||
01 00 01 3c
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|
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01 00 01 78
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01 00 01 4a
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01 00 01 07
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01 00 01 0e
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01 00 01 09
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01 00 01 1b
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01 00 01 1e
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01 00 01 0f
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|
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00 00 01 e1
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01 00 01 00
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01 00 01 22
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01 00 01 24
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01 00 01 06
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01 00 01 12
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01 00 01 07
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01 00 01 36
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01 00 01 47
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01 00 01 47
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01 00 01 06
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01 00 01 0a
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01 00 01 07
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01 00 01 30
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01 00 01 37
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01 00 01 0f
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||||
|
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00 00 01 c0
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01 00 01 10
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01 00 01 10
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||||
|
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00 00 01 c1
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01 00 01 41
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||||
|
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00 00 01 c5
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01 00 01 00
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01 00 01 22
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01 00 01 80
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||||
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||||
00 00 01 36
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01 00 01 48
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||||
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00 00 01 3a
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01 00 01 66 /*
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* interface pixel format:
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* 66 for RGB3x8(8bit)
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* 55 for RGB565(16bit)
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*/
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00 00 01 b0
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01 00 01 00
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00 00 01 b1
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01 00 01 70 /*
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* frame rate control:
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* 70 (45hz) for RGB3x8(8bit)
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* a0 (60hz) for RGB565(16bit)
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*/
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01 00 01 11
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00 00 01 b4
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01 00 01 02
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00 00 01 B6
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01 00 01 02 /*
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* display function control:
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* 32 for RGB
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* 02 for MCU
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||||
*/
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01 00 01 02
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00 00 01 b7
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01 00 01 c6
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||||
|
||||
00 00 01 be
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01 00 01 00
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||||
01 00 01 04
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||||
|
||||
00 00 01 e9
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01 00 01 00
|
||||
|
||||
00 00 01 f7
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||||
01 00 01 a9
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||||
01 00 01 51
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||||
01 00 01 2c
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01 00 01 82
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||||
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00 78 01 11
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00 32 01 29
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||||
00 00 01 2c
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];
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panel-exit-sequence = [
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||||
//type delay num val1 val2 val3
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00 0a 01 28
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00 78 01 10
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];
|
||||
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display-timings {
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native-mode = <&kd050fwfba002_timing>;
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kd050fwfba002_timing: timing0 {
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/*
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* 7840125 for frame rate 45Hz
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* 10453500 for frame rate 60Hz
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*/
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clock-frequency = <7840125>;
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hactive = <320>;
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vactive = <480>;
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hback-porch = <10>;
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hfront-porch = <5>;
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vback-porch = <10>;
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vfront-porch = <5>;
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hsync-len = <10>;
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vsync-len = <10>;
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hsync-active = <0>;
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vsync-active = <0>;
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de-active = <0>;
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pixelclk-active = <1>;
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};
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};
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port {
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panel_in_rgb: endpoint {
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remote-endpoint = <&rgb_out_panel>;
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};
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};
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};
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ports {
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rgb_out: port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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rgb_out_panel: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&panel_in_rgb>;
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};
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};
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};
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};
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&rgb_in_vop {
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status = "okay";
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};
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&route_rgb {
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status = "disabled";
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};
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/*
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* The pins of sdmmc1 and lcd are multiplexed
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*/
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&sdio {
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status = "disabled";
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};
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&sdio_pwrseq {
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status = "disabled";
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};
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&vop {
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status = "okay";
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/*
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* Default config is as follows:
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*
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* mcu-pix-total = <9>;
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* mcu-cs-pst = <1>;
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* mcu-cs-pend = <8>;
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* mcu-rw-pst = <2>;
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* mcu-rw-pend = <5>;
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* mcu-hold-mode = <0>; // default set to 0
|
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*
|
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* To increase the frame rate, reduce all parameters because
|
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* the max dclk rate of mcu is 150M in rv1103/rv1106.
|
||||
*/
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mcu-timing {
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mcu-pix-total = <5>;
|
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mcu-cs-pst = <1>;
|
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mcu-cs-pend = <4>;
|
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mcu-rw-pst = <2>;
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mcu-rw-pend = <3>;
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|
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mcu-hold-mode = <0>; // default set to 0
|
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};
|
||||
};
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@@ -89,6 +89,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
|
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-demo1-lp4-v10.dtb
|
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-demo4-ddr4-v10.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-demo4-ddr4-v10-linux.dtb
|
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-demo6-ddr3-v10.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-evb1-ddr4-v10.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-evb1-ddr4-v10-linux.dtb
|
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-evb1-ddr4-v10-spi-nand-linux.dtb
|
||||
|
||||
22
arch/arm64/boot/dts/rockchip/rk3528-demo6-ddr3-v10.dts
Normal file
22
arch/arm64/boot/dts/rockchip/rk3528-demo6-ddr3-v10.dts
Normal file
@@ -0,0 +1,22 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "rk3528-demo6-ddr3-v10.dtsi"
|
||||
#include "rk3528-android.dtsi"
|
||||
|
||||
&pdm {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&pdm_clk1
|
||||
&pdm_sdi1>;
|
||||
};
|
||||
|
||||
&pdmics {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pdm_mic_array {
|
||||
status = "okay";
|
||||
};
|
||||
337
arch/arm64/boot/dts/rockchip/rk3528-demo6-ddr3-v10.dtsi
Normal file
337
arch/arm64/boot/dts/rockchip/rk3528-demo6-ddr3-v10.dtsi
Normal file
@@ -0,0 +1,337 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "rk3528.dtsi"
|
||||
#include "rk3528-demo.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Rockchip RK3528 DEMO6 DDR3 V10 Board";
|
||||
compatible = "rockchip,rk3528-demo6-ddr3-v10", "rockchip,rk3528";
|
||||
|
||||
/delete-node/ vcc-ddr-s3;
|
||||
/delete-node/ vcc-3v3-s3;
|
||||
/delete-node/ vdd-cpu;
|
||||
/delete-node/ vdd-logic;
|
||||
/delete-node/ vdd-0v9-s3;
|
||||
/delete-node/ vdd-1v8-s3;
|
||||
|
||||
/omit-if-no-ref/
|
||||
vcc_sd: vcc-sd {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-boot-on;
|
||||
gpio = <&gpio4 RK_PA1 GPIO_ACTIVE_LOW>;
|
||||
regulator-name = "vcc_sd";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc_3v3_s3>;
|
||||
};
|
||||
|
||||
sdio_pwrseq: sdio-pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wifi_enable_h &clkm1_32k_out>;
|
||||
reset-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
vccio_sd: vccio-sd {
|
||||
compatible = "regulator-gpio";
|
||||
regulator-name = "vccio_sd";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
states = <1800000 0x0
|
||||
3300000 0x1>;
|
||||
};
|
||||
|
||||
wireless_bluetooth: wireless-bluetooth {
|
||||
compatible = "bluetooth-platdata";
|
||||
//wifi-bt-power-toggle;
|
||||
uart_rts_gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default", "rts_gpio";
|
||||
pinctrl-0 = <&uart2m1_rtsn &bt_enable_h>;
|
||||
pinctrl-1 = <&uart2m1_gpios>;
|
||||
BT,reset_gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
|
||||
BT,wake_gpio = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>;
|
||||
BT,wake_host_irq = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
wireless_wlan: wireless-wlan {
|
||||
compatible = "wlan-platdata";
|
||||
rockchip,grf = <&grf>;
|
||||
wifi_chip_type = "aic8800";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wifi_host_wake_irq >;
|
||||
WIFI,host_wake_irq = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
|
||||
//WIFI,reset_gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
/* Use rgmii-rxid mode to disable rx delay inside Soc */
|
||||
phy-mode = "rgmii-rxid";
|
||||
clock_in_out = "output";
|
||||
|
||||
snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 20ms, 100ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
|
||||
tx_delay = <0x30>;
|
||||
/* rx_delay = <0x3f>; */
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rgmii_miim
|
||||
&rgmii_tx_bus2
|
||||
&rgmii_rx_bus2
|
||||
&rgmii_rgmii_clk
|
||||
&rgmii_rgmii_bus
|
||||
ð_pins>;
|
||||
|
||||
phy-handle = <&rgmii_phy>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
rk805: rk805@18 {
|
||||
compatible = "rockchip,rk805";
|
||||
status = "okay";
|
||||
reg = <0x18>;
|
||||
interrupt-parent = <&gpio4>;
|
||||
interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int_l>;
|
||||
wakeup-source;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "rk805-clkout1", "rk805-clkout2";
|
||||
rk805,system-power-controoler;
|
||||
|
||||
vcc1-supply = <&vcc5v0_sys>;
|
||||
vcc2-supply = <&vcc5v0_sys>;
|
||||
vcc3-supply = <&vcc5v0_sys>;
|
||||
vcc4-supply = <&vcc5v0_sys>;
|
||||
vcc5-supply = <&vcc_3v3_s3>;
|
||||
vcc6-supply = <&vcc5v0_sys>;
|
||||
|
||||
rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pwrkey {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
regulators {
|
||||
vdd_cpu: DCDC_REG1 {
|
||||
regulator-name = "vdd_cpu";
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1450000>;
|
||||
regulator-init-microvolt = <953000>;
|
||||
regulator-initial-mode = <0x1>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_logic: DCDC_REG2 {
|
||||
regulator-name = "vdd_logic";
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1450000>;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x1>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-state-mem {
|
||||
regulator-mode = <0x2>;
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <712500>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr_s3: DCDC_REG3 {
|
||||
regulator-name = "vcc_ddr_s3";
|
||||
regulator-initial-mode = <0x1>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-state-mem {
|
||||
regulator-mode = <0x2>;
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3_s3: DCDC_REG4 {
|
||||
regulator-name = "vcc_3v3_s3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-initial-mode = <0x1>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-state-mem {
|
||||
regulator-mode = <0x2>;
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_1v8_s3: LDO_REG1 {
|
||||
regulator-name = "vdd_1v8_s3";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_18emmc: LDO_REG2 {
|
||||
regulator-name = "vcc_18emmc";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_0v9_s3: LDO_REG3 {
|
||||
regulator-name = "vdd_0v9_s3";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <900000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mdio1 {
|
||||
rgmii_phy: phy@1 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x1>;
|
||||
clocks = <&cru CLK_GMAC1_VPU_25M>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
pmic {
|
||||
pmic_int_l: pmic-int-l {
|
||||
rockchip,pins =
|
||||
<4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio-pwrseq {
|
||||
wifi_enable_h: wifi-enable-h {
|
||||
rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
wireless-wlan {
|
||||
wifi_host_wake_irq: wifi-host-wake-irq {
|
||||
rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
};
|
||||
|
||||
wireless-bluetooth {
|
||||
uart2m1_gpios: uart2m1-gpios {
|
||||
rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
bt_enable_h: bt-enable-h {
|
||||
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&rockchip_suspend {
|
||||
status = "okay";
|
||||
rockchip,sleep-mode-config = <
|
||||
(0
|
||||
|RKPM_SLP_ARMOFF
|
||||
)
|
||||
>;
|
||||
};
|
||||
|
||||
&sdio0 {
|
||||
max-frequency = <200000000>;
|
||||
no-sd;
|
||||
no-mmc;
|
||||
supports-sdio;
|
||||
bus-width = <4>;
|
||||
disable-wp;
|
||||
cap-sd-highspeed;
|
||||
cap-sdio-irq;
|
||||
keep-power-in-suspend;
|
||||
non-removable;
|
||||
mmc-pwrseq = <&sdio_pwrseq>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
|
||||
post-power-on-delay-ms = <50>;
|
||||
/delete-property/ rockchip,use-v2-tuning;
|
||||
sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
bus-width = <4>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
disable-wp;
|
||||
max-frequency = <150000000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
|
||||
rockchip,default-sample-phase = <90>;
|
||||
supports-sd;
|
||||
sd-uhs-sdr12;
|
||||
sd-uhs-sdr25;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
vmmc-supply = <&vcc_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart2m1_xfer &uart2m1_ctsn>;
|
||||
};
|
||||
@@ -1916,6 +1916,8 @@
|
||||
rockchip,hw-tshut-temp = <120000>;
|
||||
rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
|
||||
rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
|
||||
nvmem-cells = <&cpu_tsadc_trim_l>, <&cpu_tsadc_trim_h>;
|
||||
nvmem-cell-names = "trim_l", "trim_h";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@@ -2316,6 +2318,12 @@
|
||||
dmc_opp_info: dmc-opp-info@3e {
|
||||
reg = <0x3e 0x6>;
|
||||
};
|
||||
cpu_tsadc_trim_l: cpu-tsadc-trim-l@44 {
|
||||
reg = <0x44 0x1>;
|
||||
};
|
||||
cpu_tsadc_trim_h: cpu-tsadc-trim-h@45 {
|
||||
reg = <0x45 0x1>;
|
||||
};
|
||||
};
|
||||
|
||||
dmac: dma-controller@ffd60000 {
|
||||
|
||||
@@ -60,8 +60,8 @@
|
||||
i2s-lrck-gpio = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
|
||||
tdm-fsync-gpio = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>;
|
||||
rockchip,tdm-multi-lanes;
|
||||
rockchip,tx-lanes = <3>;
|
||||
rockchip,rx-lanes = <2>;
|
||||
rockchip,tdm-tx-lanes = <3>;
|
||||
rockchip,tdm-rx-lanes = <2>;
|
||||
rockchip,clk-trcm = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@@ -48,6 +48,18 @@
|
||||
vin-supply = <&avcc_1v8_s0>;
|
||||
};
|
||||
|
||||
vcc3v3_pcie_wifi: vcc3v3-pcie-wifi {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_pcie_wifi";
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
enable-active-high;
|
||||
gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
|
||||
startup-delay-us = <5000>;
|
||||
vin-supply = <&vcc_3v3_s0>;
|
||||
};
|
||||
|
||||
vcc5v0_host: vcc5v0-host {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_host";
|
||||
@@ -62,6 +74,19 @@
|
||||
//pinctrl-0 = <&vcc5v0_host_en>;
|
||||
//TODO: should powered by MCU
|
||||
};
|
||||
|
||||
wireless_bluetooth: wireless-bluetooth {
|
||||
compatible = "bluetooth-platdata";
|
||||
BT,reset_gpio = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
wireless_wlan: wireless-wlan {
|
||||
compatible = "wlan-platdata";
|
||||
wifi_chip_type = "ap6398s";
|
||||
WIFI,poweren_gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&combphy0_ps {
|
||||
@@ -142,7 +167,10 @@
|
||||
};
|
||||
|
||||
&pcie2x1l2 {
|
||||
reset-gpios = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>;
|
||||
rockchip,skip-scan-in-resume;
|
||||
rockchip,perst-inactive-ms = <500>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie_wifi>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@@ -164,6 +192,12 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1m1_xfer &uart1m1_ctsn &uart1m1_rtsn>;
|
||||
};
|
||||
|
||||
&u2phy1_otg {
|
||||
phy-supply = <&vcc5v0_host>;
|
||||
};
|
||||
|
||||
@@ -5,14 +5,6 @@
|
||||
*/
|
||||
|
||||
/ {
|
||||
lt7911d {
|
||||
compatible = "lontium,lt7911d-fb-notifier";
|
||||
reset-gpios = <&gpio0 RK_PD2 GPIO_ACTIVE_LOW>,
|
||||
<&gpio4 RK_PA7 GPIO_ACTIVE_LOW>,
|
||||
<&gpio3 RK_PD4 GPIO_ACTIVE_LOW>,
|
||||
<&gpio3 RK_PD2 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
dsi2lvds_backlight1: dsi2lvds_backlight1 {
|
||||
compatible = "pwm-backlight";
|
||||
brightness-levels = <
|
||||
@@ -1015,6 +1007,13 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
lt7911d@2b {
|
||||
compatible = "lontium,lt7911d-fb-notifier";
|
||||
reg = <0x2b>;
|
||||
reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
@@ -1206,6 +1205,13 @@
|
||||
reset-gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_LOW>;
|
||||
ilitek,name = "ilitek_i2c";
|
||||
};
|
||||
|
||||
lt7911d@2b {
|
||||
compatible = "lontium,lt7911d-fb-notifier";
|
||||
reg = <0x2b>;
|
||||
reset-gpios = <&gpio0 RK_PD2 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&i2c6 {
|
||||
@@ -1593,6 +1599,13 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
lt7911d@2b {
|
||||
compatible = "lontium,lt7911d-fb-notifier";
|
||||
reg = <0x2b>;
|
||||
reset-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&i2c8 {
|
||||
@@ -1769,6 +1782,13 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
lt7911d@2b {
|
||||
compatible = "lontium,lt7911d-fb-notifier";
|
||||
reg = <0x2b>;
|
||||
reset-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&mipi_dcphy0 {
|
||||
@@ -1918,25 +1938,25 @@
|
||||
};
|
||||
|
||||
&vop {
|
||||
assigned-clocks = <&cru PLL_V0PLL>;
|
||||
assigned-clock-rates = <1152000000>;
|
||||
//assigned-clocks = <&cru PLL_V0PLL>;
|
||||
//assigned-clock-rates = <1152000000>;
|
||||
};
|
||||
|
||||
//dp01
|
||||
&vp0 {
|
||||
assigned-clocks = <&cru DCLK_VOP0_SRC>;
|
||||
assigned-clock-parents = <&cru PLL_V0PLL>;
|
||||
assigned-clock-parents = <&cru PLL_GPLL>;
|
||||
};
|
||||
|
||||
//edp01
|
||||
&vp1 {
|
||||
assigned-clocks = <&cru DCLK_VOP1_SRC>;
|
||||
assigned-clock-parents = <&cru PLL_GPLL>;
|
||||
};
|
||||
|
||||
//dsi0
|
||||
&vp2 {
|
||||
assigned-clocks = <&cru DCLK_VOP2_SRC>;
|
||||
assigned-clock-parents = <&cru PLL_V0PLL>;
|
||||
};
|
||||
|
||||
//dsi1
|
||||
&vp3 {
|
||||
assigned-clocks = <&cru DCLK_VOP3>;
|
||||
assigned-clock-parents = <&cru PLL_V0PLL>;
|
||||
|
||||
@@ -895,6 +895,17 @@ config VIDEO_OS02G10
|
||||
This is a Video4Linux2 sensor driver for the OmniVision
|
||||
OS02G10 camera.
|
||||
|
||||
config VIDEO_OS02K10
|
||||
tristate "OmniVision OS02K10 sensor support"
|
||||
depends on I2C && VIDEO_DEV
|
||||
depends on MEDIA_CAMERA_SUPPORT
|
||||
select MEDIA_CONTROLLER
|
||||
select VIDEO_V4L2_SUBDEV_API
|
||||
select V4L2_FWNODE
|
||||
help
|
||||
This is a Video4Linux2 sensor driver for the OmniVision
|
||||
OS02K10 camera.
|
||||
|
||||
config VIDEO_OS03B10
|
||||
tristate "OmniVision OS03B10 sensor support"
|
||||
depends on I2C && VIDEO_DEV
|
||||
|
||||
@@ -134,6 +134,7 @@ obj-$(CONFIG_VIDEO_NVP6188) += nvp6188.o
|
||||
obj-$(CONFIG_VIDEO_NVP6324) += jaguar1_drv/
|
||||
obj-$(CONFIG_VIDEO_OG01A1B) += og01a1b.o
|
||||
obj-$(CONFIG_VIDEO_OS02G10) += os02g10.o
|
||||
obj-$(CONFIG_VIDEO_OS02K10) += os02k10.o
|
||||
obj-$(CONFIG_VIDEO_OS03B10) += os03b10.o
|
||||
obj-$(CONFIG_VIDEO_OS04A10) += os04a10.o
|
||||
obj-$(CONFIG_VIDEO_OS05A20) += os05a20.o
|
||||
|
||||
2262
drivers/media/i2c/os02k10.c
Normal file
2262
drivers/media/i2c/os02k10.c
Normal file
File diff suppressed because it is too large
Load Diff
@@ -737,7 +737,9 @@ run_next:
|
||||
}
|
||||
}
|
||||
|
||||
/* read 3d lut at frame end */
|
||||
/* disable isp force update to read 3dlut
|
||||
* 3dlut auto update at frame end for single sensor
|
||||
*/
|
||||
if (hw->is_single && is_upd &&
|
||||
rkisp_read_reg_cache(dev, ISP_3DLUT_UPDATE) & 0x1) {
|
||||
rkisp_unite_write(dev, ISP_3DLUT_UPDATE, 0, true, hw->is_unite);
|
||||
@@ -4031,9 +4033,14 @@ void rkisp_isp_isr(unsigned int isp_mis,
|
||||
}
|
||||
|
||||
if (IS_HDR_RDBK(dev->hdr.op_mode)) {
|
||||
/* read 3d lut at isp readback */
|
||||
if (!dev->hw_dev->is_single)
|
||||
rkisp_write(dev, ISP_3DLUT_UPDATE, 0, true);
|
||||
/* disabled frame end to read 3dlut for multi sensor
|
||||
* 3dlut will update at isp readback
|
||||
*/
|
||||
if (!dev->hw_dev->is_single) {
|
||||
writel(0, hw->base_addr + ISP_3DLUT_UPDATE);
|
||||
if (hw->is_unite)
|
||||
writel(0, hw->base_next_addr + ISP_3DLUT_UPDATE);
|
||||
}
|
||||
rkisp_stats_rdbk_enable(&dev->stats_vdev, true);
|
||||
goto vs_skip;
|
||||
}
|
||||
|
||||
@@ -341,11 +341,11 @@ static const struct reg_sequence rk3588_udphy_init_sequence[] = {
|
||||
{0x0D2C, 0xFF}, {0x1D2C, 0xFF},
|
||||
{0x0D34, 0x0F}, {0x1D34, 0x0F},
|
||||
{0x08FC, 0x2A}, {0x0914, 0x28},
|
||||
{0x0A30, 0x03}, {0x0E38, 0x05},
|
||||
{0x0A30, 0x03}, {0x0E38, 0x03},
|
||||
{0x0ECC, 0x27}, {0x0ED0, 0x22},
|
||||
{0x0ED4, 0x26}, {0x18FC, 0x2A},
|
||||
{0x1914, 0x28}, {0x1A30, 0x03},
|
||||
{0x1E38, 0x05}, {0x1ECC, 0x27},
|
||||
{0x1E38, 0x03}, {0x1ECC, 0x27},
|
||||
{0x1ED0, 0x22}, {0x1ED4, 0x26},
|
||||
{0x0048, 0x0F}, {0x0060, 0x3C},
|
||||
{0x0064, 0xF7}, {0x006C, 0x20},
|
||||
|
||||
@@ -647,40 +647,40 @@ static const struct tsadc_table rk3399_code_table[] = {
|
||||
static const struct tsadc_table rk3528_code_table[] = {
|
||||
{0, MIN_TEMP},
|
||||
{1386, MIN_TEMP},
|
||||
{1419, -40000},
|
||||
{1427, -35000},
|
||||
{1435, -30000},
|
||||
{1443, -25000},
|
||||
{1452, -20000},
|
||||
{1460, -15000},
|
||||
{1468, -10000},
|
||||
{1477, -5000},
|
||||
{1486, 0},
|
||||
{1494, 5000},
|
||||
{1502, 10000},
|
||||
{1510, 15000},
|
||||
{1519, 20000},
|
||||
{1527, 25000},
|
||||
{1535, 30000},
|
||||
{1544, 35000},
|
||||
{1552, 40000},
|
||||
{1561, 45000},
|
||||
{1569, 50000},
|
||||
{1578, 55000},
|
||||
{1586, 60000},
|
||||
{1594, 65000},
|
||||
{1603, 70000},
|
||||
{1612, 75000},
|
||||
{1620, 80000},
|
||||
{1410, -40000},
|
||||
{1419, -35000},
|
||||
{1428, -30000},
|
||||
{1436, -25000},
|
||||
{1445, -20000},
|
||||
{1454, -15000},
|
||||
{1463, -10000},
|
||||
{1471, -5000},
|
||||
{1480, 0},
|
||||
{1489, 5000},
|
||||
{1498, 10000},
|
||||
{1506, 15000},
|
||||
{1515, 20000},
|
||||
{1524, 25000},
|
||||
{1533, 30000},
|
||||
{1541, 35000},
|
||||
{1550, 40000},
|
||||
{1558, 45000},
|
||||
{1567, 50000},
|
||||
{1575, 55000},
|
||||
{1584, 60000},
|
||||
{1593, 65000},
|
||||
{1602, 70000},
|
||||
{1610, 75000},
|
||||
{1619, 80000},
|
||||
{1628, 85000},
|
||||
{1637, 90000},
|
||||
{1646, 95000},
|
||||
{1654, 100000},
|
||||
{1662, 105000},
|
||||
{1671, 110000},
|
||||
{1679, 115000},
|
||||
{1688, 120000},
|
||||
{1696, 125000},
|
||||
{1663, 105000},
|
||||
{1672, 110000},
|
||||
{1680, 115000},
|
||||
{1689, 120000},
|
||||
{1697, 125000},
|
||||
{1790, MAX_TEMP},
|
||||
{TSADCV5_DATA_MASK, MAX_TEMP},
|
||||
};
|
||||
@@ -1489,8 +1489,6 @@ static int rk_tsadcv3_get_trim_code(const struct chip_tsadc_table *table,
|
||||
int temp = trim_base * 1000 + trim_base_frac * 100;
|
||||
u32 base_code = rk_tsadcv2_temp_to_code(table, temp);
|
||||
|
||||
rk_tsadcv2_temp_to_code(table, temp);
|
||||
|
||||
return (TSADCV3_Q_MAX_VAL - code) - base_code;
|
||||
}
|
||||
|
||||
@@ -1872,6 +1870,8 @@ static const struct rockchip_tsadc_chip rk3528_tsadc_data = {
|
||||
.set_alarm_temp = rk_tsadcv3_alarm_temp,
|
||||
.set_tshut_temp = rk_tsadcv3_tshut_temp,
|
||||
.set_tshut_mode = rk_tsadcv4_tshut_mode,
|
||||
.get_trim_code = rk_tsadcv3_get_trim_code,
|
||||
.trim_slope = 574,
|
||||
|
||||
.table = {
|
||||
.id = rk3528_code_table,
|
||||
|
||||
@@ -851,6 +851,7 @@ int rga_request_release_signal(struct rga_scheduler_t *scheduler, struct rga_job
|
||||
struct rga_pending_request_manager *request_manager;
|
||||
struct rga_request *request;
|
||||
int finished_count, failed_count;
|
||||
bool is_finished = false;
|
||||
unsigned long flags;
|
||||
|
||||
request_manager = rga_drvdata->pend_request_manager;
|
||||
@@ -899,7 +900,7 @@ int rga_request_release_signal(struct rga_scheduler_t *scheduler, struct rga_job
|
||||
|
||||
rga_dma_fence_signal(request->release_fence, request->ret);
|
||||
|
||||
wake_up(&request->finished_wq);
|
||||
is_finished = true;
|
||||
|
||||
if (DEBUGGER_EN(MSG))
|
||||
pr_info("request[%d] finished %d failed %d\n",
|
||||
@@ -912,7 +913,12 @@ int rga_request_release_signal(struct rga_scheduler_t *scheduler, struct rga_job
|
||||
}
|
||||
|
||||
mutex_lock(&request_manager->lock);
|
||||
|
||||
if (is_finished)
|
||||
wake_up(&request->finished_wq);
|
||||
|
||||
rga_request_put(request);
|
||||
|
||||
mutex_unlock(&request_manager->lock);
|
||||
|
||||
return 0;
|
||||
|
||||
@@ -1582,6 +1582,53 @@ static int rga_mm_get_handle_info(struct rga_job *job)
|
||||
req = &job->rga_command_base;
|
||||
mm = rga_drvdata->mm;
|
||||
|
||||
switch (req->render_mode) {
|
||||
case BITBLT_MODE:
|
||||
case COLOR_PALETTE_MODE:
|
||||
if (unlikely(req->src.yrgb_addr <= 0)) {
|
||||
pr_err("render_mode[0x%x] src0 channel handle[%ld] must is valid!",
|
||||
req->render_mode, (unsigned long)req->src.yrgb_addr);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (unlikely(req->dst.yrgb_addr <= 0)) {
|
||||
pr_err("render_mode[0x%x] dst channel handle[%ld] must is valid!",
|
||||
req->render_mode, (unsigned long)req->dst.yrgb_addr);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (req->bsfilter_flag) {
|
||||
if (unlikely(req->pat.yrgb_addr <= 0)) {
|
||||
pr_err("render_mode[0x%x] src1/pat channel handle[%ld] must is valid!",
|
||||
req->render_mode, (unsigned long)req->pat.yrgb_addr);
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
break;
|
||||
case COLOR_FILL_MODE:
|
||||
if (unlikely(req->dst.yrgb_addr <= 0)) {
|
||||
pr_err("render_mode[0x%x] dst channel handle[%ld] must is valid!",
|
||||
req->render_mode, (unsigned long)req->dst.yrgb_addr);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
case UPDATE_PALETTE_TABLE_MODE:
|
||||
case UPDATE_PATTEN_BUF_MODE:
|
||||
if (unlikely(req->pat.yrgb_addr <= 0)) {
|
||||
pr_err("render_mode[0x%x] lut/pat channel handle[%ld] must is valid!, req->render_mode",
|
||||
req->render_mode, (unsigned long)req->pat.yrgb_addr);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
break;
|
||||
default:
|
||||
pr_err("%s, unknown render mode!\n", __func__);
|
||||
break;
|
||||
}
|
||||
|
||||
if (likely(req->src.yrgb_addr > 0)) {
|
||||
ret = rga_mm_get_channel_handle_info(mm, job, &req->src,
|
||||
&job->src_buffer,
|
||||
|
||||
Reference in New Issue
Block a user