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[ARM] tegra: Add i2c support
Signed-off-by: Colin Cross <ccross@android.com>
This commit is contained in:
Colin Cross
@@ -596,6 +596,13 @@ config I2C_STU300
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This driver can also be built as a module. If so, the module
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will be called i2c-stu300.
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config I2C_TEGRA
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tristate "NVIDIA Tegra internal I2C controller"
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depends on ARCH_TEGRA
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help
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If you say yes to this option, support will be included for the
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I2C controller embedded in NVIDIA Tegra SOCs
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config I2C_VERSATILE
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tristate "ARM Versatile/Realview I2C bus support"
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depends on ARCH_VERSATILE || ARCH_REALVIEW || ARCH_VEXPRESS
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@@ -57,6 +57,7 @@ obj-$(CONFIG_I2C_SH7760) += i2c-sh7760.o
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obj-$(CONFIG_I2C_SH_MOBILE) += i2c-sh_mobile.o
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obj-$(CONFIG_I2C_SIMTEC) += i2c-simtec.o
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obj-$(CONFIG_I2C_STU300) += i2c-stu300.o
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obj-$(CONFIG_I2C_TEGRA) += i2c-tegra.o
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obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o
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obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o
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obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o
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640
drivers/i2c/busses/i2c-tegra.c
Normal file
640
drivers/i2c/busses/i2c-tegra.c
Normal file
@@ -0,0 +1,640 @@
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/*
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* drivers/i2c/busses/i2c-tegra.c
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*
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* Copyright (C) 2010 Google, Inc.
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* Author: Colin Cross <ccross@android.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/i2c.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <asm/unaligned.h>
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#define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000))
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#define BYTES_PER_FIFO_WORD 4
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#define I2C_CNFG 0x000
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#define I2C_CNFG_PACKET_MODE_EN (1<<10)
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#define I2C_CNFG_NEW_MASTER_FSM (1<<11)
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#define I2C_SL_CNFG 0x020
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#define I2C_SL_CNFG_NEWSL (1<<2)
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#define I2C_SL_ADDR1 0x02c
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#define I2C_TX_FIFO 0x050
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#define I2C_RX_FIFO 0x054
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#define I2C_PACKET_TRANSFER_STATUS 0x058
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#define I2C_FIFO_CONTROL 0x05c
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#define I2C_FIFO_CONTROL_TX_FLUSH (1<<1)
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#define I2C_FIFO_CONTROL_RX_FLUSH (1<<0)
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#define I2C_FIFO_CONTROL_TX_TRIG_SHIFT 5
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#define I2C_FIFO_CONTROL_RX_TRIG_SHIFT 2
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#define I2C_FIFO_STATUS 0x060
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#define I2C_FIFO_STATUS_TX_MASK 0xF0
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#define I2C_FIFO_STATUS_TX_SHIFT 4
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#define I2C_FIFO_STATUS_RX_MASK 0x0F
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#define I2C_FIFO_STATUS_RX_SHIFT 0
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#define I2C_INT_MASK 0x064
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#define I2C_INT_STATUS 0x068
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#define I2C_INT_PACKET_XFER_COMPLETE (1<<7)
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#define I2C_INT_ALL_PACKETS_XFER_COMPLETE (1<<6)
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#define I2C_INT_TX_FIFO_OVERFLOW (1<<5)
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#define I2C_INT_RX_FIFO_UNDERFLOW (1<<4)
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#define I2C_INT_NO_ACK (1<<3)
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#define I2C_INT_ARBITRATION_LOST (1<<2)
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#define I2C_INT_TX_FIFO_DATA_REQ (1<<1)
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#define I2C_INT_RX_FIFO_DATA_REQ (1<<0)
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#define I2C_CLK_DIVISOR 0x06c
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#define DVC_CTRL_REG1 0x000
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#define DVC_CTRL_REG1_INTR_EN (1<<10)
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#define DVC_CTRL_REG2 0x004
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#define DVC_CTRL_REG3 0x008
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#define DVC_CTRL_REG3_SW_PROG (1<<26)
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#define DVC_CTRL_REG3_I2C_DONE_INTR_EN (1<<30)
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#define I2C_ERR_NONE 0x00
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#define I2C_ERR_NO_ACK 0x01
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#define I2C_ERR_ARBITRATION_LOST 0x02
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#define PACKET_HEADER0_HEADER_SIZE_SHIFT 28
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#define PACKET_HEADER0_PACKET_ID_SHIFT 16
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#define PACKET_HEADER0_CONT_ID_SHIFT 12
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#define PACKET_HEADER0_PROTOCOL_I2C (1<<4)
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#define I2C_HEADER_HIGHSPEED_MODE (1<<22)
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#define I2C_HEADER_CONT_ON_NAK (1<<21)
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#define I2C_HEADER_SEND_START_BYTE (1<<20)
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#define I2C_HEADER_READ (1<<19)
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#define I2C_HEADER_10BIT_ADDR (1<<18)
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#define I2C_HEADER_IE_ENABLE (1<<17)
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#define I2C_HEADER_REPEAT_START (1<<16)
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#define I2C_HEADER_MASTER_ADDR_SHIFT 12
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#define I2C_HEADER_SLAVE_ADDR_SHIFT 1
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struct tegra_i2c_dev {
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struct device *dev;
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struct i2c_adapter adapter;
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struct clk *clk;
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struct clk *i2c_clk;
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struct resource *iomem;
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void __iomem *base;
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int cont_id;
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int irq;
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int is_dvc;
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struct completion msg_complete;
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int msg_err;
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u8 *msg_buf;
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size_t msg_buf_remaining;
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int msg_read;
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int msg_transfer_complete;
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};
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static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg)
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{
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writel(val, i2c_dev->base + reg);
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}
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static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
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{
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return readl(i2c_dev->base + reg);
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}
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/* i2c_writel and i2c_readl will offset the register if necessary to talk
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* to the I2C block inside the DVC block
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*/
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static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg)
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{
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if (i2c_dev->is_dvc)
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reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
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writel(val, i2c_dev->base + reg);
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}
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static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
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{
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if (i2c_dev->is_dvc)
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reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
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return readl(i2c_dev->base + reg);
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}
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static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
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{
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u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
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int_mask &= ~mask;
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i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
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}
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static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
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{
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u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
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int_mask |= mask;
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i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
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}
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static void tegra_i2c_set_clk(struct tegra_i2c_dev *i2c_dev, unsigned int freq)
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{
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u32 val;
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unsigned long input_freq = clk_get_rate(i2c_dev->i2c_clk);
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val = input_freq / 12 / freq - 1;
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dev_dbg(i2c_dev->dev, "clock %lu to %u: %x\n", input_freq, freq, val);
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dev_dbg(i2c_dev->dev, "clock was %x\n", i2c_readl(i2c_dev, I2C_CLK_DIVISOR));
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i2c_writel(i2c_dev, val, I2C_CLK_DIVISOR);
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dev_dbg(i2c_dev->dev, "clock is %x\n", i2c_readl(i2c_dev, I2C_CLK_DIVISOR));
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}
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static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
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{
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unsigned long timeout = jiffies + HZ;
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u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL);
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val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH;
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i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
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while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) &
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(I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) {
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if (time_after(jiffies, timeout)) {
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dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
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return -ETIMEDOUT;
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}
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msleep(1);
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}
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return 0;
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}
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static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
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{
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u32 val;
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int rx_fifo_avail;
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int word;
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u8 *buf = i2c_dev->msg_buf;
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size_t buf_remaining = i2c_dev->msg_buf_remaining;
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int words_to_transfer;
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val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
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rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >>
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I2C_FIFO_STATUS_RX_SHIFT;
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words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
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if (words_to_transfer > rx_fifo_avail)
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words_to_transfer = rx_fifo_avail;
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for (word=0; word < words_to_transfer; word++) {
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val = i2c_readl(i2c_dev, I2C_RX_FIFO);
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put_unaligned_le32(val, buf);
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buf += BYTES_PER_FIFO_WORD;
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buf_remaining -= BYTES_PER_FIFO_WORD;
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rx_fifo_avail--;
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}
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if (rx_fifo_avail > 0 && buf_remaining > 0) {
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int bytes_to_transfer = buf_remaining;
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int byte;
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BUG_ON(bytes_to_transfer > 3);
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val = i2c_readl(i2c_dev, I2C_RX_FIFO);
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for (byte = 0; byte < bytes_to_transfer; byte++) {
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*buf++ = val & 0xFF;
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val >>= 8;
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}
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buf_remaining -= bytes_to_transfer;
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rx_fifo_avail--;
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}
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BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0);
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i2c_dev->msg_buf_remaining = buf_remaining;
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i2c_dev->msg_buf = buf;
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return 0;
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}
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static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
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{
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u32 val;
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int tx_fifo_avail;
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int word;
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u8 *buf = i2c_dev->msg_buf;
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size_t buf_remaining = i2c_dev->msg_buf_remaining;
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int words_to_transfer;
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val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
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tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >>
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I2C_FIFO_STATUS_TX_SHIFT;
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words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
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if (words_to_transfer > tx_fifo_avail)
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words_to_transfer = tx_fifo_avail;
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dev_dbg(i2c_dev->dev, "fill_tx_fifo: tx_fifo_avail %d\n", tx_fifo_avail);
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dev_dbg(i2c_dev->dev, "fill_tx_fifo: words_to_transfer %d\n", words_to_transfer);
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for (word=0; word < words_to_transfer; word++) {
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val = get_unaligned_le32(buf);
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i2c_writel(i2c_dev, val, I2C_TX_FIFO);
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buf += BYTES_PER_FIFO_WORD;
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buf_remaining -= BYTES_PER_FIFO_WORD;
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tx_fifo_avail--;
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}
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if (tx_fifo_avail > 0 && buf_remaining > 0) {
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int bytes_to_transfer = buf_remaining;
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int byte;
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dev_dbg(i2c_dev->dev, "fill_tx_fifo: bytes_to_transfer %d\n", bytes_to_transfer);
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BUG_ON(bytes_to_transfer > 3);
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val = 0;
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for (byte = 0; byte < bytes_to_transfer; byte++) {
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val |= (*buf++) << (byte * 8);
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}
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i2c_writel(i2c_dev, val, I2C_TX_FIFO);
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buf_remaining -= bytes_to_transfer;
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tx_fifo_avail--;
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}
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BUG_ON(tx_fifo_avail > 0 && buf_remaining > 0);
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i2c_dev->msg_buf_remaining = buf_remaining;
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i2c_dev->msg_buf = buf;
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return 0;
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}
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/* One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
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* block. This block is identical to the rest of the I2C blocks, except that
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* it only supports master mode, it has registers moved around, and it needs
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* some extra init to get it into I2C mode. The register moves are handled
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* by i2c_readl and i2c_writel
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*/
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static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
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{
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u32 val = 0;
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val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
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val |= DVC_CTRL_REG3_SW_PROG;
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val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
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dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
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val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
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val |= DVC_CTRL_REG1_INTR_EN;
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dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
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val = I2C_SL_CNFG_NEWSL;
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i2c_writel(i2c_dev, val, I2C_SL_CNFG);
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val = 0xF;
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i2c_writel(i2c_dev, val, I2C_SL_ADDR1);
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}
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static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
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{
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u32 val;
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clk_enable(i2c_dev->clk);
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clk_enable(i2c_dev->i2c_clk);
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if (i2c_dev->is_dvc)
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tegra_dvc_init(i2c_dev);
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val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN;
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i2c_writel(i2c_dev, val, I2C_CNFG);
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i2c_writel(i2c_dev, 0, I2C_INT_MASK);
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tegra_i2c_set_clk(i2c_dev, 100000);
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val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT |
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0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT;
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i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
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if (tegra_i2c_flush_fifos(i2c_dev))
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return -ETIMEDOUT;
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return 0;
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}
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static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
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{
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u32 status;
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const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
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struct tegra_i2c_dev *i2c_dev = dev_id;
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status = i2c_readl(i2c_dev, I2C_INT_STATUS);
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if (status == 0) {
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printk("irq status 0 %08x\n", i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS));
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//BUG();
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return IRQ_HANDLED;
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}
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dev_dbg(i2c_dev->dev, "irq status %02x\n", status);
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dev_dbg(i2c_dev->dev, "irq mask %02x\n", i2c_readl(i2c_dev, I2C_INT_MASK));
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dev_dbg(i2c_dev->dev, "transfer: %08x fifo %02x\n", i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS), i2c_readl(i2c_dev, I2C_FIFO_STATUS));
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dev_dbg(i2c_dev->dev, "remaining: %d\n", i2c_dev->msg_buf_remaining);
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dev_dbg(i2c_dev->dev, "xfer complete: %d \n", i2c_dev->msg_transfer_complete);
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if (unlikely(status & status_err)) {
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if (status & I2C_INT_NO_ACK)
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i2c_dev->msg_err |= I2C_ERR_NO_ACK;
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if (status & I2C_INT_ARBITRATION_LOST)
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i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
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complete(&i2c_dev->msg_complete);
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goto err;
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}
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if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
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if (i2c_dev->msg_buf_remaining)
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tegra_i2c_empty_rx_fifo(i2c_dev);
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else
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BUG();
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}
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|
||||
if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
|
||||
if (i2c_dev->msg_buf_remaining)
|
||||
tegra_i2c_fill_tx_fifo(i2c_dev);
|
||||
else
|
||||
tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ);
|
||||
}
|
||||
|
||||
if (status & I2C_INT_PACKET_XFER_COMPLETE)
|
||||
i2c_dev->msg_transfer_complete = 1;
|
||||
|
||||
if (i2c_dev->msg_transfer_complete && !i2c_dev->msg_buf_remaining)
|
||||
complete(&i2c_dev->msg_complete);
|
||||
i2c_writel(i2c_dev, status, I2C_INT_STATUS);
|
||||
return IRQ_HANDLED;
|
||||
err:
|
||||
/* An error occured, mask all interrupts */
|
||||
tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
|
||||
I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
|
||||
I2C_INT_RX_FIFO_DATA_REQ);
|
||||
i2c_writel(i2c_dev, status, I2C_INT_STATUS);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
|
||||
struct i2c_msg *msg, int stop)
|
||||
{
|
||||
u32 packet_header;
|
||||
u32 int_mask;
|
||||
int ret;
|
||||
|
||||
tegra_i2c_flush_fifos(i2c_dev);
|
||||
i2c_writel(i2c_dev, 0xFF, I2C_INT_STATUS);
|
||||
|
||||
dev_dbg(i2c_dev->dev, "%s: addr 0x%04x, len %d, flags 0x%x, stop %d\n",
|
||||
__func__, msg->addr, msg->len, msg->flags, stop);
|
||||
if (msg->len == 0)
|
||||
return -EINVAL;
|
||||
|
||||
i2c_dev->msg_buf = msg->buf;
|
||||
i2c_dev->msg_buf_remaining = msg->len;
|
||||
i2c_dev->msg_err = I2C_ERR_NONE;
|
||||
i2c_dev->msg_transfer_complete = 0;
|
||||
i2c_dev->msg_read = (msg->flags & I2C_M_RD);
|
||||
INIT_COMPLETION(i2c_dev->msg_complete);
|
||||
|
||||
packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
|
||||
PACKET_HEADER0_PROTOCOL_I2C |
|
||||
(i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
|
||||
(1 << PACKET_HEADER0_PACKET_ID_SHIFT);
|
||||
i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
|
||||
|
||||
packet_header = msg->len - 1;
|
||||
i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
|
||||
|
||||
packet_header = msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
|
||||
packet_header |= I2C_HEADER_IE_ENABLE;
|
||||
if (msg->flags & I2C_M_TEN)
|
||||
packet_header |= I2C_HEADER_10BIT_ADDR;
|
||||
if (msg->flags & I2C_M_IGNORE_NAK)
|
||||
packet_header |= I2C_HEADER_CONT_ON_NAK;
|
||||
if (msg->flags & I2C_M_NOSTART)
|
||||
packet_header |= I2C_HEADER_REPEAT_START;
|
||||
if (msg->flags & I2C_M_RD)
|
||||
packet_header |= I2C_HEADER_READ;
|
||||
i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
|
||||
|
||||
if (!(msg->flags & I2C_M_RD))
|
||||
tegra_i2c_fill_tx_fifo(i2c_dev);
|
||||
|
||||
dev_dbg(i2c_dev->dev, "before transfer: %08x fifo %02x\n", i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS), i2c_readl(i2c_dev, I2C_FIFO_STATUS));
|
||||
|
||||
int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
|
||||
if (msg->flags & I2C_M_RD)
|
||||
int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
|
||||
else if (i2c_dev->msg_buf_remaining)
|
||||
int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
|
||||
tegra_i2c_unmask_irq(i2c_dev, int_mask);
|
||||
pr_debug("unmasked irq: %02x\n", i2c_readl(i2c_dev, I2C_INT_MASK));
|
||||
|
||||
ret = wait_for_completion_timeout(&i2c_dev->msg_complete, TEGRA_I2C_TIMEOUT);
|
||||
tegra_i2c_mask_irq(i2c_dev, int_mask);
|
||||
|
||||
dev_dbg(i2c_dev->dev, "after transfer: %08x fifo %02x\n", i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS), i2c_readl(i2c_dev, I2C_FIFO_STATUS));
|
||||
if (ret == 0) {
|
||||
dev_err(i2c_dev->dev, "i2c transfer timed out\n");
|
||||
dev_err(i2c_dev->dev, "");
|
||||
BUG();
|
||||
tegra_i2c_init(i2c_dev);
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
pr_debug("transfer complete: %d %d %d\n", ret, completion_done(&i2c_dev->msg_complete), i2c_dev->msg_err);
|
||||
|
||||
if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
|
||||
return 0;
|
||||
BUG();
|
||||
tegra_i2c_init(i2c_dev);
|
||||
if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
|
||||
if (msg->flags & I2C_M_IGNORE_NAK)
|
||||
return 0;
|
||||
return -EREMOTEIO;
|
||||
}
|
||||
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
|
||||
{
|
||||
struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
|
||||
int i;
|
||||
for (i = 0; i < num; i++) {
|
||||
int stop = (i == (num - 1)) ? 1 : 0;
|
||||
tegra_i2c_xfer_msg(i2c_dev, &msgs[i], stop);
|
||||
}
|
||||
|
||||
return num;
|
||||
}
|
||||
|
||||
static u32 tegra_i2c_func(struct i2c_adapter *adap)
|
||||
{
|
||||
/* FIXME: For now keep it simple and don't support protocol mangling
|
||||
features */
|
||||
return I2C_FUNC_I2C;
|
||||
}
|
||||
|
||||
static const struct i2c_algorithm tegra_i2c_algo = {
|
||||
.master_xfer = tegra_i2c_xfer,
|
||||
.functionality = tegra_i2c_func,
|
||||
};
|
||||
|
||||
static int tegra_i2c_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct tegra_i2c_dev *i2c_dev;
|
||||
/*struct tegra_i2c_platform_data *pdata = pdev->dev.platform_data;*/
|
||||
struct resource *res;
|
||||
struct resource *iomem;
|
||||
struct clk *clk;
|
||||
struct clk *i2c_clk;
|
||||
void *base;
|
||||
int irq;
|
||||
int ret = 0;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res) {
|
||||
dev_err(&pdev->dev, "no mem resource?\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
iomem = request_mem_region(res->start, resource_size(res), pdev->name);
|
||||
if (!iomem) {
|
||||
dev_err(&pdev->dev, "I2C region already claimed\n");
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
base = ioremap(iomem->start, resource_size(iomem));
|
||||
if (!base) {
|
||||
dev_err(&pdev->dev, "Can't ioremap I2C region\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
||||
if (!res) {
|
||||
dev_err(&pdev->dev, "no irq resource?\n");
|
||||
ret = -ENODEV;
|
||||
goto err_iounmap;
|
||||
}
|
||||
irq = res->start;
|
||||
|
||||
clk = clk_get(&pdev->dev, NULL);
|
||||
if (!clk) {
|
||||
ret = -ENOMEM;
|
||||
goto err_release_region;
|
||||
}
|
||||
|
||||
i2c_clk = clk_get(&pdev->dev, "i2c");
|
||||
if (!i2c_clk) {
|
||||
ret = -ENOMEM;
|
||||
goto err_clk_put;
|
||||
}
|
||||
|
||||
i2c_dev = kzalloc(sizeof(struct tegra_i2c_dev), GFP_KERNEL);
|
||||
if (!i2c_dev) {
|
||||
ret = -ENOMEM;
|
||||
goto err_i2c_clk_put;
|
||||
}
|
||||
|
||||
i2c_dev->base = base;
|
||||
i2c_dev->clk = clk;
|
||||
i2c_dev->i2c_clk = i2c_clk;
|
||||
i2c_dev->iomem = iomem;
|
||||
i2c_dev->adapter.algo = &tegra_i2c_algo;
|
||||
i2c_dev->irq = irq;
|
||||
i2c_dev->cont_id = pdev->id;
|
||||
i2c_dev->dev = &pdev->dev;
|
||||
init_completion(&i2c_dev->msg_complete);
|
||||
|
||||
platform_set_drvdata(pdev, i2c_dev);
|
||||
|
||||
ret = tegra_i2c_init(i2c_dev);
|
||||
if (ret)
|
||||
goto err_free;
|
||||
|
||||
|
||||
ret = request_irq(i2c_dev->irq, tegra_i2c_isr, IRQF_DISABLED,
|
||||
pdev->name, i2c_dev);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
|
||||
goto err_free;
|
||||
}
|
||||
|
||||
i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
|
||||
i2c_dev->adapter.owner = THIS_MODULE;
|
||||
i2c_dev->adapter.class = I2C_CLASS_HWMON;
|
||||
strlcpy(i2c_dev->adapter.name, "Tegra I2C adapter",
|
||||
sizeof(i2c_dev->adapter.name));
|
||||
i2c_dev->adapter.algo = &tegra_i2c_algo;
|
||||
i2c_dev->adapter.dev.parent = &pdev->dev;
|
||||
i2c_dev->adapter.nr = pdev->id;
|
||||
if (pdev->id == 3)
|
||||
i2c_dev->is_dvc = 1;
|
||||
|
||||
|
||||
ret = i2c_add_numbered_adapter(&i2c_dev->adapter);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Failed to add I2C adapter\n");
|
||||
goto err_free_irq;
|
||||
}
|
||||
|
||||
return 0;
|
||||
err_free_irq:
|
||||
free_irq(i2c_dev->irq, i2c_dev);
|
||||
err_free:
|
||||
kfree(i2c_dev);
|
||||
err_i2c_clk_put:
|
||||
clk_put(i2c_clk);
|
||||
err_clk_put:
|
||||
clk_put(clk);
|
||||
err_release_region:
|
||||
release_mem_region(iomem->start, resource_size(iomem));
|
||||
err_iounmap:
|
||||
iounmap(base);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int tegra_i2c_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
|
||||
i2c_del_adapter(&i2c_dev->adapter);
|
||||
free_irq(i2c_dev->irq, i2c_dev);
|
||||
clk_put(i2c_dev->i2c_clk);
|
||||
clk_put(i2c_dev->clk);
|
||||
release_mem_region(i2c_dev->iomem->start, resource_size(i2c_dev->iomem));
|
||||
iounmap(i2c_dev->base);
|
||||
kfree(i2c_dev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra_i2c_suspend(struct platform_device *pdev, pm_message_t state)
|
||||
{
|
||||
/* FIXME to be implemented */
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra_i2c_resume(struct platform_device *pdev)
|
||||
{
|
||||
/* FIXME to be implemented */
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver tegra_i2c_driver = {
|
||||
.probe = tegra_i2c_probe,
|
||||
.remove = tegra_i2c_remove,
|
||||
.suspend = tegra_i2c_suspend,
|
||||
.resume = tegra_i2c_resume,
|
||||
.driver =
|
||||
{
|
||||
.name = "tegra-i2c",
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init tegra_i2c_init_driver(void)
|
||||
{
|
||||
return platform_driver_register(&tegra_i2c_driver);
|
||||
}
|
||||
module_init(tegra_i2c_init_driver);
|
||||
|
||||
static void __exit tegra_i2c_exit_driver(void)
|
||||
{
|
||||
platform_driver_unregister(&tegra_i2c_driver);
|
||||
}
|
||||
module_exit(tegra_i2c_exit_driver);
|
||||
Reference in New Issue
Block a user