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clk: rockchip: rk3588: use COMPOSITE_DCLK for dclk_vp2

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div = DIV_ROUND_UP_ULL(400000000, rate);

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I6106b9e661db21392af3185c4d3a1f17cd5d844f
This commit is contained in:
Elaine Zhang
2021-11-22 10:14:56 +08:00
committed by Tao Huang
parent 7534ec9a51
commit cb1f0723c1
1 changed files with 3 additions and 2 deletions
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5
drivers/clk/rockchip/clk-rk3588.c
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@@ -15,6 +15,7 @@
#define RK3588_GRF_SOC_STATUS0 0x600
#define RK3588_FRAC_MAX_PRATE 1500000000
#define RK3588_DCLK_MAX_PRATE 400000000
enum rk3588_plls {
b0pll, b1pll, lpll, v0pll, aupll, cpll, gpll, npll, ppll,
@@ -2185,9 +2186,9 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
COMPOSITE(DCLK_VOP1_SRC, "dclk_vop1_src", gpll_cpll_v0pll_aupll_p, 0,
RK3588_CLKSEL_CON(111), 14, 2, MFLAGS, 9, 5, DFLAGS,
RK3588_CLKGATE_CON(52), 11, GFLAGS),
COMPOSITE(DCLK_VOP2_SRC, "dclk_vop2_src", gpll_cpll_v0pll_aupll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
COMPOSITE_DCLK(DCLK_VOP2_SRC, "dclk_vop2_src", gpll_cpll_v0pll_aupll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
RK3588_CLKSEL_CON(112), 5, 2, MFLAGS, 0, 5, DFLAGS,
RK3588_CLKGATE_CON(52), 12, GFLAGS),
RK3588_CLKGATE_CON(52), 12, GFLAGS, RK3588_DCLK_MAX_PRATE),
COMPOSITE_NODIV(DCLK_VOP0, "dclk_vop0", dclk_vop0_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
RK3588_CLKSEL_CON(112), 7, 2, MFLAGS,
RK3588_CLKGATE_CON(52), 13, GFLAGS),