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rk2818 for linux2.6.32

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This commit is contained in:
林辉辉
2010-04-22 04:26:22 +00:00
committed by 黄涛
parent 16fe6f1aa7
commit cb338334b9
35 changed files with 3815 additions and 3 deletions
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1481
.config Normal file
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File diff suppressed because it is too large Load Diff

7
Makefile
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@@ -180,8 +180,11 @@ SUBARCH := $(shell uname -m | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ \
# Default value for CROSS_COMPILE is not to prefix executables
# Note: Some architectures assign CROSS_COMPILE in their arch/*/Makefile
export KBUILD_BUILDHOST := $(SUBARCH)
ARCH ?= $(SUBARCH)
CROSS_COMPILE ?=
#ARCH ?= $(SUBARCH)
#CROSS_COMPILE ?=
ARCH ?= arm
#CROSS_COMPILE :=/opt/android0320/mydroid/prebuilt/linux-x86/toolchain/arm-eabi-4.2.1/bin/arm-eabi-
CROSS_COMPILE ?=../toolchain/arm-eabi-4.2.1/bin/arm-eabi-
# Architecture as present in compile.h
UTS_MACHINE := $(ARCH)

10
arch/arm/Kconfig
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@@ -701,6 +701,15 @@ config ARCH_BCMRING
select ARCH_WANT_OPTIONAL_GPIOLIB
help
Support for Broadcom's BCMRing platform.
config ARCH_RK2818
bool "Rockchip soc rk2818"
select CPU_ARM926T
select CPU_CP15_MMU
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
help
Support for Rockchip RK2818 soc.
endchoice
@@ -803,6 +812,7 @@ source "arch/arm/mach-u300/Kconfig"
source "arch/arm/mach-w90x900/Kconfig"
source "arch/arm/mach-bcmring/Kconfig"
source "arch/arm/mach-rk2818/Kconfig"
# Definitions to make life easier
config ARCH_ACORN

1
arch/arm/Makefile
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@@ -170,6 +170,7 @@ machine-$(CONFIG_ARCH_VERSATILE) := versatile
machine-$(CONFIG_ARCH_W90X900) := w90x900
machine-$(CONFIG_FOOTBRIDGE) := footbridge
machine-$(CONFIG_ARCH_MXC91231) := mxc91231
machine-$(CONFIG_ARCH_RK2818) := rk2818
# Platform directory name. This list is sorted alphanumerically
# by CONFIG_* macro name.

13
arch/arm/mach-rk2818/Kconfig Normal file
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@@ -0,0 +1,13 @@
if ARCH_RK2818
comment "ROCKCHIP rk2818 Board Type"
depends on ARCH_RK2818
config MACH_RK2818MID
depends on ARCH_RK2818
default y
bool "ROCKCHIP Board For Mid"
help
Support for the ROCKCHIP Board For Rk2818 Mid.
endif

8
arch/arm/mach-rk2818/Makefile Normal file
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@@ -0,0 +1,8 @@
obj-y += io.o idle.o irq.o timer.o
obj-y += devices.o
obj-y += proc_comm.o
obj-y += vreg.o
obj-y += clock.o clock-rk2818.o
obj-$(CONFIG_MACH_RK2818MID) += board-midsdk.o

3
arch/arm/mach-rk2818/Makefile.boot Normal file
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@@ -0,0 +1,3 @@
zreladdr-y := 0x10008000
params_phys-y := 0x10000100
initrd_phys-y := 0x10800000

106
arch/arm/mach-rk2818/board-midsdk.c Normal file
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@@ -0,0 +1,106 @@
/* linux/arch/arm/mach-rk2818/board-midsdk.c
*
* Copyright (C) 2010 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/input.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/flash.h>
#include <mach/irqs.h>
#include <mach/board.h>
#include <mach/rk2818_iomap.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include "devices.h"
//IOӳ<4F>䷽ʽ<E4B7BD><CABD><EFBFBD><EFBFBD> <20><>ÿ<EFBFBD><C3BF>Ϊһ<CEAA><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ӳ<EFBFBD><D3B3>
static struct map_desc rk2818_io_desc[] __initdata = {
{
.virtual = RK2818_AHB_BASE, //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ
.pfn = __phys_to_pfn(RK2818_AHB_PHYS), //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ҳ<EFBFBD><D2B3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
.length = RK2818_AHB_SIZE, //<2F><><EFBFBD><EFBFBD>
.type = MT_DEVICE //ӳ<>䷽ʽ
},
{
.virtual = RK2818_APB_BASE,
.pfn = __phys_to_pfn(RK2818_APB_PHYS),
.length = RK2818_APB_SIZE,
.type = MT_DEVICE
},
{
.virtual = RK2818_DSP_BASE,
.pfn = __phys_to_pfn(RK2818_DSP_PHYS),
.length = RK2818_DSP_SIZE,
.type = MT_DEVICE
},
{
.virtual = 0xff400000, /* for itcm , vir = phy , for reboot */
.pfn = __phys_to_pfn(0xff400000),
.length = SZ_16K,
.type = MT_DEVICE
}
};
static struct platform_device *devices[] __initdata = {
//&rk2818_add_device_serial,
};
extern struct sys_timer rk2818_timer;
static void __init machine_rk2818_init_irq(void)
{
rk2818_init_irq();
}
static void __init machine_rk2818_board_init(void)
{
platform_add_devices(devices, ARRAY_SIZE(devices));
}
static void __init machine_rk2818_mapio(void)
{
iotable_init(rk2818_io_desc, ARRAY_SIZE(rk2818_io_desc));
rk2818_clock_init();
//rk2818_iomux_init();
/* Setup the serial ports and console*/
// rk2818_init_serial(&rk2818_uart_config);
}
MACHINE_START(RK2818, "rk2818midsdk")
/* UART for LL DEBUG */
.phys_io = 0x18002000,
.io_pg_offst = ((0xFF100000) >> 18) & 0xfffc,
.boot_params = RK2818_SDRAM_PHYS + 0x100,
.map_io = machine_rk2818_mapio,
.init_irq = machine_rk2818_init_irq,
.init_machine = machine_rk2818_board_init,
.timer = &rk2818_timer,
MACHINE_END

111
arch/arm/mach-rk2818/clock-rk2818.c Normal file
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@@ -0,0 +1,111 @@
/* arch/arm/mach-rk2818/clock-rk2818.c
*
*
* Copyright (C) 2010 Rockchip, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include "clock.h"
#include "devices.h"
/* clock IDs used by the modem processor */
#define ACPU_CLK 0 /* Applications processor clock */
#define ADM_CLK 1 /* Applications data mover clock */
#define ADSP_CLK 2 /* ADSP clock */
#define EBI1_CLK 3 /* External bus interface 1 clock */
#define EBI2_CLK 4 /* External bus interface 2 clock */
#define ECODEC_CLK 5 /* External CODEC clock */
#define EMDH_CLK 6 /* External MDDI host clock */
#define GP_CLK 7 /* General purpose clock */
#define GRP_CLK 8 /* Graphics clock */
#define I2C_CLK 9 /* I2C clock */
#define ICODEC_RX_CLK 10 /* Internal CODEX RX clock */
#define ICODEC_TX_CLK 11 /* Internal CODEX TX clock */
#define IMEM_CLK 12 /* Internal graphics memory clock */
#define MDC_CLK 13 /* MDDI client clock */
#define MDP_CLK 14 /* Mobile display processor clock */
#define PBUS_CLK 15 /* Peripheral bus clock */
#define PCM_CLK 16 /* PCM clock */
#define PMDH_CLK 17 /* Primary MDDI host clock */
#define SDAC_CLK 18 /* Stereo DAC clock */
#define SDC1_CLK 19 /* Secure Digital Card clocks */
#define SDC1_PCLK 20
#define SDC2_CLK 21
#define SDC2_PCLK 22
#define SDC3_CLK 23
#define SDC3_PCLK 24
#define SDC4_CLK 25
#define SDC4_PCLK 26
#define TSIF_CLK 27 /* Transport Stream Interface clocks */
#define TSIF_REF_CLK 28
#define TV_DAC_CLK 29 /* TV clocks */
#define TV_ENC_CLK 30
#define UART1_CLK 31 /* UART clocks */
#define UART2_CLK 32
#define UART3_CLK 33
#define UART1DM_CLK 34
#define UART2DM_CLK 35
#define USB_HS_CLK 36 /* High speed USB core clock */
#define USB_HS_PCLK 37 /* High speed USB pbus clock */
#define USB_OTG_CLK 38 /* Full speed USB clock */
#define VDC_CLK 39 /* Video controller clock */
#define VFE_CLK 40 /* Camera / Video Front End clock */
#define VFE_MDC_CLK 41 /* VFE MDDI client clock */
#define NR_CLKS 42
#define CLOCK(clk_name, clk_id, clk_dev, clk_flags) { \
.name = clk_name, \
.id = clk_id, \
.flags = clk_flags, \
.dev = clk_dev, \
}
#define OFF CLKFLAG_AUTO_OFF
#define MINMAX CLKFLAG_USE_MIN_MAX_TO_SET
struct clk rk2818_clocks[] = {
CLOCK("adm_clk", ADM_CLK, NULL, 0),
CLOCK("adsp_clk", ADSP_CLK, NULL, 0),
CLOCK("ebi1_clk", EBI1_CLK, NULL, 0),
CLOCK("ebi2_clk", EBI2_CLK, NULL, 0),
CLOCK("ecodec_clk", ECODEC_CLK, NULL, 0),
CLOCK("emdh_clk", EMDH_CLK, NULL, OFF),
CLOCK("gp_clk", GP_CLK, NULL, 0),
CLOCK("grp_clk", GRP_CLK, NULL, OFF),
CLOCK("icodec_rx_clk", ICODEC_RX_CLK, NULL, 0),
CLOCK("icodec_tx_clk", ICODEC_TX_CLK, NULL, 0),
CLOCK("imem_clk", IMEM_CLK, NULL, OFF),
CLOCK("mdc_clk", MDC_CLK, NULL, 0),
CLOCK("mdp_clk", MDP_CLK, NULL, OFF),
CLOCK("pbus_clk", PBUS_CLK, NULL, 0),
CLOCK("pcm_clk", PCM_CLK, NULL, 0),
CLOCK("pmdh_clk", PMDH_CLK, NULL, OFF | MINMAX),
CLOCK("sdac_clk", SDAC_CLK, NULL, OFF),
CLOCK("tsif_clk", TSIF_CLK, NULL, 0),
CLOCK("tsif_ref_clk", TSIF_REF_CLK, NULL, 0),
CLOCK("tv_dac_clk", TV_DAC_CLK, NULL, 0),
CLOCK("tv_enc_clk", TV_ENC_CLK, NULL, 0),
///CLOCK("uart_clk", UART1_CLK, &rk2818_device_uart1.dev, OFF),
CLOCK("uart1dm_clk", UART1DM_CLK, NULL, OFF),
CLOCK("uart2dm_clk", UART2DM_CLK, NULL, 0),
CLOCK("usb_otg_clk", USB_OTG_CLK, NULL, 0),
CLOCK("vdc_clk", VDC_CLK, NULL, OFF | MINMAX),
CLOCK("vfe_clk", VFE_CLK, NULL, OFF),
CLOCK("vfe_mdc_clk", VFE_MDC_CLK, NULL, OFF),
};
unsigned rk2818_num_clocks = ARRAY_SIZE(rk2818_clocks);

217
arch/arm/mach-rk2818/clock.c Normal file
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@@ -0,0 +1,217 @@
/* arch/arm/mach-rk2818/clock.c
*
* Copyright (C) 2010 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/version.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/list.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/spinlock.h>
#include "clock.h"
#include "proc_comm.h"
static DEFINE_MUTEX(clocks_mutex);
static DEFINE_SPINLOCK(clocks_lock);
static LIST_HEAD(clocks);
/*
* glue for the proc_comm interface
*/
static inline int pc_clk_enable(unsigned id)
{
return rk2818_proc_comm(PCOM_CLKCTL_RPC_ENABLE, &id, NULL);
}
static inline void pc_clk_disable(unsigned id)
{
rk2818_proc_comm(PCOM_CLKCTL_RPC_DISABLE, &id, NULL);
}
static inline int pc_clk_set_rate(unsigned id, unsigned rate)
{
return rk2818_proc_comm(PCOM_CLKCTL_RPC_SET_RATE, &id, &rate);
}
static inline int pc_clk_set_min_rate(unsigned id, unsigned rate)
{
return rk2818_proc_comm(PCOM_CLKCTL_RPC_MIN_RATE, &id, &rate);
}
static inline int pc_clk_set_max_rate(unsigned id, unsigned rate)
{
return rk2818_proc_comm(PCOM_CLKCTL_RPC_MAX_RATE, &id, &rate);
}
static inline int pc_clk_set_flags(unsigned id, unsigned flags)
{
return rk2818_proc_comm(PCOM_CLKCTL_RPC_SET_FLAGS, &id, &flags);
}
static inline unsigned pc_clk_get_rate(unsigned id)
{
if (rk2818_proc_comm(PCOM_CLKCTL_RPC_RATE, &id, NULL))
return 0;
else
return id;
}
static inline unsigned pc_clk_is_enabled(unsigned id)
{
if (rk2818_proc_comm(PCOM_CLKCTL_RPC_ENABLED, &id, NULL))
return 0;
else
return id;
}
static inline int pc_pll_request(unsigned id, unsigned on)
{
on = !!on;
return rk2818_proc_comm(PCOM_CLKCTL_RPC_PLL_REQUEST, &id, &on);
}
/*
* Standard clock functions defined in include/linux/clk.h
*/
struct clk *clk_get(struct device *dev, const char *id)
{
struct clk *clk;
mutex_lock(&clocks_mutex);
list_for_each_entry(clk, &clocks, list)
if (!strcmp(id, clk->name) && clk->dev == dev)
goto found_it;
list_for_each_entry(clk, &clocks, list)
if (!strcmp(id, clk->name) && clk->dev == NULL)
goto found_it;
clk = ERR_PTR(-ENOENT);
found_it:
mutex_unlock(&clocks_mutex);
return clk;
}
EXPORT_SYMBOL(clk_get);
void clk_put(struct clk *clk)
{
}
EXPORT_SYMBOL(clk_put);
int clk_enable(struct clk *clk)
{
unsigned long flags;
spin_lock_irqsave(&clocks_lock, flags);
clk->count++;
if (clk->count == 1)
pc_clk_enable(clk->id);
spin_unlock_irqrestore(&clocks_lock, flags);
return 0;
}
EXPORT_SYMBOL(clk_enable);
void clk_disable(struct clk *clk)
{
unsigned long flags;
spin_lock_irqsave(&clocks_lock, flags);
BUG_ON(clk->count == 0);
clk->count--;
if (clk->count == 0)
pc_clk_disable(clk->id);
spin_unlock_irqrestore(&clocks_lock, flags);
}
EXPORT_SYMBOL(clk_disable);
unsigned long clk_get_rate(struct clk *clk)
{
return pc_clk_get_rate(clk->id);
}
EXPORT_SYMBOL(clk_get_rate);
int clk_set_rate(struct clk *clk, unsigned long rate)
{
int ret;
if (clk->flags & CLKFLAG_USE_MIN_MAX_TO_SET) {
ret = pc_clk_set_max_rate(clk->id, rate);
if (ret)
return ret;
return pc_clk_set_min_rate(clk->id, rate);
}
return pc_clk_set_rate(clk->id, rate);
}
EXPORT_SYMBOL(clk_set_rate);
int clk_set_parent(struct clk *clk, struct clk *parent)
{
return -ENOSYS;
}
EXPORT_SYMBOL(clk_set_parent);
struct clk *clk_get_parent(struct clk *clk)
{
return ERR_PTR(-ENOSYS);
}
EXPORT_SYMBOL(clk_get_parent);
int clk_set_flags(struct clk *clk, unsigned long flags)
{
if (clk == NULL || IS_ERR(clk))
return -EINVAL;
return pc_clk_set_flags(clk->id, flags);
}
EXPORT_SYMBOL(clk_set_flags);
void __init rk2818_clock_init(void)
{
unsigned n;
spin_lock_init(&clocks_lock);
mutex_lock(&clocks_mutex);
for (n = 0; n < rk2818_num_clocks; n++)
list_add_tail(&rk2818_clocks[n].list, &clocks);
mutex_unlock(&clocks_mutex);
}
/* The bootloader and/or AMSS may have left various clocks enabled.
* Disable any clocks that belong to us (CLKFLAG_AUTO_OFF) but have
* not been explicitly enabled by a clk_enable() call.
*/
static int __init clock_late_init(void)
{
unsigned long flags;
struct clk *clk;
unsigned count = 0;
mutex_lock(&clocks_mutex);
list_for_each_entry(clk, &clocks, list) {
if (clk->flags & CLKFLAG_AUTO_OFF) {
spin_lock_irqsave(&clocks_lock, flags);
if (!clk->count) {
count++;
pc_clk_disable(clk->id);
}
spin_unlock_irqrestore(&clocks_lock, flags);
}
}
mutex_unlock(&clocks_mutex);
pr_info("clock_late_init() disabled %d unused clocks\n", count);
return 0;
}
late_initcall(clock_late_init);

47
arch/arm/mach-rk2818/clock.h Normal file
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@@ -0,0 +1,47 @@
/* arch/arm/mach-rk2818/clock.h
*
* Copyright (C) 2010 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __ARCH_ARM_MACH_RK2818_CLOCK_H
#define __ARCH_ARM_MACH_RK2818_CLOCK_H
#include <linux/list.h>
#define CLKFLAG_INVERT 0x00000001
#define CLKFLAG_NOINVERT 0x00000002
#define CLKFLAG_NONEST 0x00000004
#define CLKFLAG_NORESET 0x00000008
#define CLK_FIRST_AVAILABLE_FLAG 0x00000100
#define CLKFLAG_USE_MIN_MAX_TO_SET 0x00000200
#define CLKFLAG_AUTO_OFF 0x00000400
struct clk {
uint32_t id;
uint32_t count;
uint32_t flags;
const char *name;
struct list_head list;
struct device *dev;
};
//#define A11S_CLK_CNTL_ADDR (MSM_CSR_BASE + 0x100)
//#define A11S_CLK_SEL_ADDR (MSM_CSR_BASE + 0x104)
//#define A11S_VDD_SVS_PLEVEL_ADDR (MSM_CSR_BASE + 0x124)
extern struct clk rk2818_clocks[];
extern unsigned rk2818_num_clocks;
#endif

48
arch/arm/mach-rk2818/devices.c Normal file
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@@ -0,0 +1,48 @@
/* arch/arm/mach-rk2818/devices.c
*
* Copyright (C) 2010 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <mach/irqs.h>
#include <mach/rk2818_iomap.h>
#include "devices.h"
#include <asm/mach/flash.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
static struct resource resources_uart1[] = {
{
.start = IRQ_NR_UART1,//INT_UART1,
.end = IRQ_NR_UART1,//INT_UART1,
.flags = IORESOURCE_IRQ,
},
{
.start = RK2818_UART1_PHYS,
.end = RK2818_UART1_PHYS + SZ_1K - 1,
.flags = IORESOURCE_MEM,
},
};
struct platform_device msm_device_uart1 = {
.name = "rk2818_serial",
.id = 0,
.num_resources = ARRAY_SIZE(resources_uart1),
.resource = resources_uart1,
};

22
arch/arm/mach-rk2818/devices.h Normal file
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@@ -0,0 +1,22 @@
/* linux/arch/arm/mach-rk2818/devices.h
*
* Copyright (C) 2010 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __ARCH_ARM_MACH_RK2818_DEVICES_H
#define __ARCH_ARM_MACH_RK2818_DEVICES_H
extern struct platform_device rk2818_device_uart1;
#endif

35
arch/arm/mach-rk2818/idle.S Normal file
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@@ -0,0 +1,35 @@
/* arch/arm/mach-rk2818/include/mach/idle.S
*
* Idle processing for MSM7K - work around bugs with SWFI.
*
* Copyright (C) 2010 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
ENTRY(arch_idle)
#ifdef CONFIG_RK2818_IDLE
mrc p15, 0, r1, c1, c0, 0 /* read current CR */
bic r0, r1, #(1 << 2) /* clear dcache bit */
bic r0, r0, #(1 << 12) /* clear icache bit */
mcr p15, 0, r0, c1, c0, 0 /* disable d/i cache */
mov r0, #0 /* prepare wfi value */
mcr p15, 0, r0, c7, c10, 0 /* flush the cache */
mcr p15, 0, r0, c7, c10, 4 /* memory barrier */
mcr p15, 0, r0, c7, c0, 4 /* wait for interrupt */
mcr p15, 0, r1, c1, c0, 0 /* restore d/i cache */
#endif
mov pc, lr

37
arch/arm/mach-rk2818/include/mach/board.h Normal file
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@@ -0,0 +1,37 @@
/* arch/arm/mach-rk2818/include/mach/board.h
*
* Copyright (C) 2010 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __ASM_ARCH_RK2818_BOARD_H
#define __ASM_ARCH_RK2818_BOARD_H
#include <linux/types.h>
/* platform device data structures */
struct RK2818_mddi_platform_data
{
void (*panel_power)(int on);
unsigned has_vsync_irq:1;
};
/* common init routines for use by arch/arm/mach-msm/board-*.c */
void __init rk2818_add_devices(void);
void __init rk2818_map_common_io(void);
void __init rk2818_init_irq(void);
void __init rk2818_init_gpio(void);
void __init rk2818_clock_init(void);
#endif

39
arch/arm/mach-rk2818/include/mach/debug-macro.S Normal file
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/* arch/arm/mach-rk2818/include/mach/debug-macro.S
*
* Copyright (C) 2010 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <mach/hardware.h>
#include <mach/rk2818_iomap.h>
.macro addruart,rx
@ see if the MMU is enabled and select appropriate base address
mrc p15, 0, \rx, c1, c0
tst \rx, #1
ldreq \rx, =RK2818_UART1_PHYS
ldrne \rx, =RK2818_UART1_BASE
.endm
.macro senduart,rd,rx
str \rd, [\rx, #0x00]
.endm
.macro waituart,rd,rx
@ wait for TX_READY
1: ldr \rd, [\rx, #0x7C]
tst \rd, #0x02
beq 1b
.endm
.macro busyuart,rd,rx
.endm

209
arch/arm/mach-rk2818/include/mach/dma.h Normal file
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/*
* arch/arm/mach-rk2818/include/mach/dma.h
*
* Copyright (C) 2010 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ASM_RK2818_DMA_H
#define __ASM_RK2818_DMA_H
#include <asm/dma.h>
#define SAR 0x000 /* Source Address Register */
#define DAR 0x008 /* Destination Address Register */
#define LLP 0x010 /* Linked List Pointer Register */
#define CTL_L 0x018 /* Control Register LOW */
#define CTL_H 0x01C /* Control Register HIGH */
#define CFG_L 0x040 /* Configuration Register */
#define CFG_H 0x044 /* Configuration Register */
#define SGR 0x048 /* Source Gather Register */
#define DSR 0x050 /* Destination Scatter Register */
#define RawTfr 0x2c0 /* Raw Status for IntTfr Interrupt */
#define RawBlock 0x2c8 /* Raw Status for IntBlock Interrupt */
#define RawSrcTran 0x2d0 /* Raw Status for IntSrcTran Interrupt */
#define RawDstTran 0x2d8 /* Raw Status for IntDstTran Interrupt */
#define RawErr 0x2e0 /* Raw Status for IntErr Interrupt */
#define StatusTfr 0x2e8 /* Status for IntTfr Interrupt */
#define StatusBlock 0x2f0 /* Status for IntBlock Interrupt */
#define StatusSrcTran 0x2f8 /* Status for IntSrcTran Interrupt */
#define StatusDstTran 0x300 /* Status for IntDstTran Interrupt */
#define StatusErr 0x308 /* Status for IntErr Interrupt */
#define MaskTfr 0x310 /*Mask for IntTfr Interrupt */
#define MaskBlock 0x318 /*Mask for IntBlock Interrupt */
#define MaskSrcTran 0x320 /*Mask for IntSrcTran Interrupt */
#define MaskDstTran 0x328 /*Mask for IntDstTran Interrupt */
#define MaskErr 0x330 /*Mask for IntErr Interrupt */
#define ClearTfr 0x338 /* Clear for IntTfr Interrupt */
#define ClearBlock 0x340 /* Clear for IntBlock Interrupt */
#define ClearSrcTran 0x348 /* Clear for IntSrcTran Interrupt */
#define ClearDstTran 0x350 /* Clear for IntDstTran Interrupt */
#define ClearErr 0x358 /* Clear for IntErr Interrupt */
#define StatusInt 0x360 /* Status for each interrupt type */
#define DmaCfgReg 0x398 /* DMA Configuration Register */
#define ChEnReg 0x3a0 /* DMA Channel Enable Register */
/* Detail CFG_L Register Description */
#define CH_PRIOR_MASK (0x7 << 5)
#define CH_PRIOR_OFFSET 5
#define CH_SUSP (0x1 << 8)
#define FIFO_EMPTY (0x1 << 9)
#define HS_SEL_DST (0x1 << 10)
#define HS_SEL_SRC (0x1 << 11)
#define LOCK_CH_L_MASK (0x3 << 12)
#define LOCK_CH_L_OFFSET 12
#define LOCK_B_L_MASK (0x3 << 14)
#define LOCK_B_L_OFFSET 14
#define LOCK_CH (0x1 << 16)
#define LOCK_B (0x1 << 17)
#define DST_HS_POL (0x1 << 18)
#define SRC_HS_POL (0x1 << 19)
#define MAX_ABRST_MASK (0x3FF << 20)
#define MAX_ABRST_OFFSET 20
#define RELOAD_SRC (0x1 << 30)
#define RELOAD_DST (0x1 << 31)
/* Detail CFG_H Register Description */
#define FCMODE (0x1 << 0)
#define FIFO_MODE (0x1 << 1)
#define PROTCTL_MASK (0x7 << 2)
#define PROTCTL_OFFSET 2
#define DS_UPD_EN (0x1 << 5)
#define SS_UPD_EN (0x1 << 6)
#define SRC_PER_MASK (0xF << 7)
#define SRC_PER_OFFSET 7
#define DST_PER_MASK (0xF << 11)
#define DST_PER_OFFSET 11
/* Detail CTL_L Register Description */
#define INT_EN (0x1 << 0)
#define DST_TR_WIDTH_MASK (0x7 << 1)
#define DST_TR_WIDTH_OFFSET 1
#define SRC_TR_WIDTH_MASK (0x7 << 4)
#define SRC_TR_WIDTH_OFFSET 4
#define DINC_MASK (0x3 << 7)
#define DINC_OFFSET 7
#define SINC_MASK (0x3 << 9)
#define SINC_OFFSET 9
#define DST_MSIZE_MASK (0x7 << 11)
#define DST_MSIZE_OFFSET 11
#define SRC_MSIZE_MASK (0x7 << 14)
#define SRC_MSIZE_OFFSET 14
#define SRC_GATHER_EN (0x1 << 17)
#define DST_SCATTER_EN (0x1 << 18)
#define TT_FC_MASK (0x7 << 20)
#define TT_FC_OFFSET 20
#define DMS_MASK (0x3 << 23)
#define DMS_OFFSET 23
#define SMS_MASK (0x3 << 25)
#define SMS_OFFSET 25
#define LLP_DST_EN (0x1 << 27)
#define LLP_SRC_EN (0x1 << 28)
#define AHBMASTER_1 0x0
#define AHBMASTER_2 0x1
#define INCREMENT 0x0
#define DECREMENT 0x1
#define NOCHANGE 0x2
#define MSIZE_1 0x0
#define MSIZE_4 0x1
#define MSIZE_8 0x2
#define MSIZE_16 0x3
#define MSIZE_32 0x4
#define TR_WIDTH_8 0x0
#define TR_WIDTH_16 0x1
#define TR_WIDTH_32 0x2
#define M2M 0x0
#define M2P 0x1
#define P2M 0x2
#define P2P 0x3
/* Detail ChEnReg Register Description */
#define CH_EN_MASK (0xF << 0)
#define CH_EN_OFFSET 0
#define CH_EN_WE_MASK (0xF << 8)
#define CH_EN_WE_OFFSET 8
/* Detail DmaCfgReg Register Description */
#define DMA_EN (0x1 << 0)
#define ROCKCHIP_DMA_CHANNELS 3
typedef enum {
DMA_PRIO_HIGH = 0,
DMA_PRIO_MEDIUM = 1,
DMA_PRIO_LOW = 2
} rockchip_dma_prio;
struct rockchip_dma_channel {
const char *name;
void (*irq_handler) (int, void *);
void (*err_handler) (int, void *, int errcode);
void *data;
unsigned int dma_mode;
struct scatterlist *sg;
unsigned int sgbc;
unsigned int sgcount;
unsigned int resbytes;
dma_addr_t LLI;
void *dma_vaddr;
unsigned int curLLI;
unsigned int lli_count;
int dma_num;
unsigned int channel_base;
};
struct LLI_INFO {
unsigned int SARx;
unsigned int DARx;
unsigned int LLPx;
unsigned int CTL_Lx;
unsigned int CTL_Hx;
// unsigned int SSATx;
// unsigned int DSATx;
};
extern struct rockchip_dma_channel rockchip_dma_channels[ROCKCHIP_DMA_CHANNELS];
int rockchip_dma_setup_single(int dma_ch, dma_addr_t dma_address,
unsigned int dma_length, unsigned int dev_addr,
unsigned int dmamode);
int rockchip_dma_setup_sg(int dma_ch,
struct scatterlist *sg, unsigned int sgcount, unsigned int dma_length,
unsigned int dev_addr, unsigned int dmamode);
int rockchip_dma_setup_handlers(int dma_ch,
void (*irq_handler) (int, void *),
void (*err_handler) (int, void *, int), void *data);
void rockchip_dma_enable(int dma_ch);
void rockchip_dma_disable(int dma_ch);
int rockchip_dma_request(int dma_ch, const char *name);
void rockchip_dma_free(int dma_ch);
int rockchip_dma_request_by_prio(const char *name, rockchip_dma_prio prio);
#endif

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arch/arm/mach-rk2818/include/mach/entry-macro.S Normal file
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/* arch/arm/mach-rk2818/include/mach/entry-macro.S
*
* Copyright (C) 2010 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include "irqs.h"
.macro disable_fiq
.endm
.macro get_irqnr_preamble, base, tmp
ldr \base,=0xff0aa000
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
1001:
ldr \irqstat, [\base, #IRQ_REG_FINALSTATUS_L]
cmp \irqstat, #0
beq 1002f
clz \irqnr, \irqstat
rsb \irqnr, \irqnr, #31
b 1003f
1002:
ldr \irqstat, [\base, #IRQ_REG_FINALSTATUS_H]
lsr \tmp, \irqstat, #8
and \tmp, \tmp, #0xff
lsl \tmp, \tmp, #8
and \irqstat, \irqstat, #0xff
orr \irqstat, \irqstat, \tmp
cmp \irqstat, #0
beq 1003f
clz \irqnr, \irqstat
rsb \irqnr, \irqnr, #31
add \irqnr, \irqnr, #32
1003:
.endm

25
arch/arm/mach-rk2818/include/mach/hardware.h Normal file
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/* arch/arm/mach-rk2818/include/mach/hardware.h
*
* Copyright (C) 2010 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __ASM_ARCH_RK2818_HARDWARE_H
#ifndef __ASSEMBLY__
# define __REG(x) (*((volatile u32 *)IO_ADDRESS(x)))
# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y)))
#endif
#endif

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arch/arm/mach-rk2818/include/mach/io.h Normal file
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/* arch/arm/mach-rk2818/include/mach/io.h
*
* Copyright (C) 2010 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#define IO_SPACE_LIMIT 0xffffffff
#define __arch_ioremap __rk2818_ioremap
#define __arch_iounmap __iounmap
void __iomem *__rk2818_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype);
static inline void __iomem *__io(unsigned long addr)
{
return (void __iomem *)addr;
}
#define __io(a) __typesafe_io(a)
#define __mem_pci(a) (a)
#endif

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arch/arm/mach-rk2818/include/mach/irqs.h Normal file
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/* arch/arm/mach-rk2818/include/mach/irqs.h
*
* Copyright (C) 2010 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __ARCH_ARM_MACH_RK2818_IRQS_H
#define __ARCH_ARM_MACH_RK2818_IRQS_H
#define IRQ_REG_INTEN_L 0x00//IRQ interrupt source enable register (low)
#define IRQ_REG_INTEN_H 0x04//IRQ interrupt source enable register (high)
#define IRQ_REG_INTMASK_L 0x08//IRQ interrupt source mask register (low).
#define IRQ_REG_INTMASK_H 0x0c//IRQ interrupt source mask register (high).
#define IRQ_REG_INTFORCE_L 0x10//IRQ interrupt force register
#define IRQ_REG_INTFORCE_H 0x14//
#define IRQ_REG_RAWSTATUS_L 0x18//IRQ raw status register
#define IRQ_REG_RAWSTATUS_H 0x1c//
#define IRQ_REG_STATUS_L 0x20//IRQ status register
#define IRQ_REG_STATUS_H 0x24//
#define IRQ_REG_MASKSTATUS_L 0x28//IRQ interrupt mask status register
#define IRQ_REG_MASKSTATUS_H 0x2c//
#define IRQ_REG_FINALSTATUS_L 0x30//IRQ interrupt final status
#define IRQ_REG_FINALSTATUS_H 0x34
#define FIQ_REG_INTEN 0xc0//Fast interrupt enable register
#define FIQ_REG_INTMASK 0xc4//Fast interrupt mask register
#define FIQ_REG_INTFORCE 0xc8//Fast interrupt force register
#define FIQ_REG_RAWSTATUS 0xcc//Fast interrupt source raw status register
#define FIQ_REG_STATUS 0xd0//Fast interrupt status register
#define FIQ_REG_FINALSTATUS 0xd4//Fast interrupt final status register
#define IRQ_REG_PLEVEL 0xd8//IRQ System Priority Level Register
#define NR_IRQS (48)
/*irq number*/
#define IRQ_NR_DWDMA 0 // -- low
#define IRQ_NR_HOST 1 // -- Host Interface
#define IRQ_NR_NANDC 2
#define IRQ_NR_LCDC 3
#define IRQ_NR_SDMMC0 4
#define IRQ_NR_VIP 5
#define IRQ_NR_GPIO0 6
#define IRQ_NR_GPIO1 7
#define IRQ_NR_OTG 8 // -- USB OTG
#define IRQ_NR_ABTARMD 9 // -- Arbiter in ARMD BUS
#define IRQ_NR_ABTEXP 10//-- Arbiter in EXP BUS
#define IRQ_NR_I2C0 11
#define IRQ_NR_I2C1 12
#define IRQ_NR_I2S 13
#define IRQ_NR_SPIM 14// -- SPI Master
#define IRQ_NR_SPIS 15//-- SPI Slave
#define IRQ_NR_TIMER1 16
#define IRQ_NR_TIMER2 17
#define IRQ_NR_TIMER3 18
#define IRQ_NR_UART0 19
#define IRQ_NR_UART1 20
#define IRQ_NR_WDT 21
#define IRQ_NR_PWM0 22
#define IRQ_NR_PWM1 23
#define IRQ_NR_PWM2 24
#define IRQ_NR_PWM3 25
#define IRQ_NR_ADC 26
#define IRQ_NR_RTC 27
#define IRQ_NR_PIUSEM0 28// -- PIU Semphore 0
#define IRQ_NR_PIUSEM1 29
#define IRQ_NR_PIUSEM3 30
#define IRQ_NR_PIUCMD 31// -- PIU command/reply
#define IRQ_NR_XDMA 32
#define IRQ_NR_SDMMC1 33
#define IRQ_NR_DSPSEI 34// -- DSP slave interface error interrupt
#define IRQ_NR_DSPSWI 35// -- DSP interrupt by software set
#define IRQ_NR_SCU 36
#define IRQ_NR_SWI 37// -- Software Interrupt
#define IRQ_NR_DSPMEI 38// -- DSP master interface error interrupt
#define IRQ_NR_DSPSAEI 39// -- DSP system access error interrupt
#define IRQ_GPU_M55_INT 40
#define IRQ_GPU_MMU_INT 41
#define IRQ_DDRII_MOBILE_CTR_INIT 42
#define IRQ_MC_DMA_INT 43
#define IRQ_NAND_FLASH_RDY_INT 44
#define IRQ_APB_UART2 45
#define IRQ_APB_UART3 46
#define IRQ_USB_HOST 47
#endif

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arch/arm/mach-rk2818/include/mach/memory.h Normal file
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/* arch/arm/mach-rk2818/include/mach/memory.h
*
* Copyright (C) 2010 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
/* physical offset of RAM */
#define PHYS_OFFSET UL(0x60000000)
/* bus address and physical addresses are identical */
#define __virt_to_bus(x) __virt_to_phys(x)
#define __bus_to_virt(x) __phys_to_virt(x)
#endif

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arch/arm/mach-rk2818/include/mach/rk2818_iomap.h Normal file
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/* arch/arm/mach-rk2818/include/mach/rk281x_iomap.h
*
* Copyright (C) 2010 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
*
*/
#ifndef __ASM_ARCH_RK2818_IOMAP_H
#define __ASM_ARCH_RK2818_IOMAP_H
#include <asm/sizes.h>
/* defines */
#define SZ_22K 0x5800
/* Physical base address and size of peripherals.
* Ordered by the virtual base addresses they will be mapped at.
*
* RK2818_VIC_BASE must be an value that can be loaded via a "mov"
* instruction, otherwise entry-macro.S will not compile.
*
* If you add or remove entries here, you'll want to edit the
* rk2818_io_desc array in arch/arm/mach-rk2818/io.c to reflect your
* changes.
*
*/
//<2F>ڴ<EFBFBD><DAB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ
#ifdef CONFIG_DRAM_BASE
#define RK2818_SDRAM_BASE 0x60000000//CONFIG_DRAM_BASE
#else
#define RK2818_SDRAM_PHYS 0x60000000
#define RK2818_SDRAM_SIZE (0x00100000*64)
#endif
#define RK2818_AHB_BASE 0xFF000000
#define RK2818_AHB_PHYS 0x10000000 //AHB <20><><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ
#define RK2818_AHB_SIZE 0x00100000 // size:1M
#define RK2818_APB_BASE 0xFF100000
#define RK2818_APB_PHYS 0x18000000 // APB<50><42><EFBFBD><EFBFBD><EFBFBD>豸<EFBFBD><E8B1B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ
#define RK2818_APB_SIZE 0x00100000 // size:1M
#define RK2818_BOOTROM_BASE 0xFF000000
#define RK2818_BOOTROM_PHYS 0x10000000
#define RK2818_BOOTROM_SIZE SZ_8K
#define RK2818_SRAM_BASE 0xFF002000
#define RK2818_SRAM_PHYS 0x10002000
#define RK2818_SRAM_SIZE SZ_8K
#define RK2818_USBOTG_BASE 0xFF040000
#define RK2818_USBOTG_PHYS 0x10040000
#define RK2818_USBOTG_SIZE SZ_256K
#define RK2818_MCDMA_BASE 0xFF080000
#define RK2818_MCDMA_PHYS 0x10080000
#define RK2818_MCDMA_SIZE SZ_8K
#define RK2818_SHAREMEM_BASE 0xFF090000
#define RK2818_SHAREMEM_PHYS 0x10090000
#define RK2818_SHAREMEM_SIZE SZ_64K
#define RK2818_DWDMA_BASE 0xFF0A0000
#define RK2818_DWDMA_PHYS 0x100A0000
#define RK2818_DWDMA_SIZE SZ_8K
#define RK2818_HOSTIF_BASE 0xFF0A2000
#define RK2818_HOSTIF_PHYS 0x100A2000
#define RK2818_HOSTIF_SIZE SZ_8K
#define RK2818_LCDC_BASE 0xFF0A4000
#define RK2818_LCDC_PHYS 0x100A4000
#define RK2818_LCDC_SIZE SZ_8K
#define RK2818_VIP_BASE 0xFF0A6000
#define RK2818_VIP_PHYS 0x100A6000
#define RK2818_VIP_SIZE SZ_8K
#define RK2818_SDMMC1_BASE 0xFF0A8000
#define RK2818_SDMMC1_PHYS 0x100A8000
#define RK2818_SDMMC1_SIZE SZ_8K
#define RK2818_INTC_BASE 0xFF0AA000
#define RK2818_INTC_PHYS 0x100AA000
#define RK2818_INTC_SIZE SZ_8K
#define RK2818_SDMMC0_BASE 0xFF0AC000
#define RK2818_SDMMC0_PHYS 0x100AC000
#define RK2818_SDMMC0_SIZE SZ_8K
#define RK2818_NANDC_BASE 0xFF0AE000
#define RK2818_NANDC_PHYS 0x100AE000
#define RK2818_NANDC_SIZE SZ_16K
#define RK2818_SDRAMC_BASE 0xFF0B0000
#define RK2818_SDRAMC_PHYS 0x100B0000
#define RK2818_SDRAMC_SIZE SZ_8K
#define RK2818_ARMDARBITER_BASE 0xFF0B4000
#define RK2818_ARMDARBITER_PHYS 0x100B4000
#define RK2818_ARMDARBITER_SIZE SZ_8K
#define RK2818_VIDEOCOP_BASE 0xFF0B8000
#define RK2818_VIDEOCOP_PHYS 0x100B8000
#define RK2818_VIDEOCOP_SIZE SZ_8K
#define RK2818_ESRAM_BASE 0xFF0BA000
#define RK2818_ESRAM_PHYS 0x100BA000
#define RK2818_ESRAM_SIZE SZ_8K
#define RK2818_USBHOST_BASE 0xFF10000
#define RK2818_USBHOST_PHYS 0x1010000
#define RK2818_USBHOST_SIZE SZ_256K
#define RK2818_UART0_BASE 0xFF100000
#define RK2818_UART0_PHYS 0x18000000
#define RK2818_UART0_SIZE SZ_4K
#define RK2818_UART2_BASE 0xFF101000
#define RK2818_UART2_PHYS 0x18001000
#define RK2818_UART2_SIZE SZ_4K
#define RK2818_UART1_BASE 0xFF102000
#define RK2818_UART1_PHYS 0x18002000
#define RK2818_UART1_SIZE SZ_4K
#define RK2818_UART3_BASE 0xFF103000
#define RK2818_UART3_PHYS 0x18003000
#define RK2818_UART3_SIZE SZ_4K
#define RK2818_TIMER_BASE 0xFF104000
#define RK2818_TIMER_PHYS 0x18004000
#define RK2818_TIMER_SIZE SZ_8K
#define RK2818_eFUSE_BASE 0xFF106000
#define RK2818_eFUSE_PHYS 0x18006000
#define RK2818_eFUSE_SIZE SZ_8K
#define RK2818_GPIO0_BASE 0xFF108000
#define RK2818_GPIO0_PHYS 0x18008000
#define RK2818_GPIO0_SIZE SZ_8K
#define RK2818_GPIO1_BASE 0xFF109000
#define RK2818_GPIO1_PHYS 0x18009000
#define RK2818_GPIO1_SIZE SZ_8K
#define RK2818_I2S_BASE 0xFF10A000
#define RK2818_I2S_PHYS 0x1800A000
#define RK2818_I2S_SIZE SZ_8K
#define RK2818_I2C0_BASE 0xFF10C000
#define RK2818_I2C0_PHYS 0x1800C000
#define RK2818_I2C0_SIZE SZ_4K
#define RK2818_I2C1_BASE 0xFF10D000
#define RK2818_I2C1_PHYS 0x1800D000
#define RK2818_I2C1_SIZE SZ_4K
#define RK2818_SPIMASTER_BASE 0xFF10E000
#define RK2818_SPIMASTER_PHYS 0x1800E000
#define RK2818_SPIMASTER_SIZE SZ_4K
#define RK2818_SPISLAVE_BASE 0xFF10F000
#define RK2818_SPISLAVE_PHYS 0x1800F000
#define RK2818_SPISLAVE_SIZE SZ_4K
#define RK2818_WDT_BASE 0xFF110000
#define RK2818_WDT_PHYS 0x18010000
#define RK2818_WDT_SIZE SZ_8K
#define RK2818_PWM_BASE 0xFF112000
#define RK2818_PWM_PHYS 0x18012000
#define RK2818_PWM_SIZE SZ_8K
#define RK2818_RTC_BASE 0xFF114000
#define RK2818_RTC_PHYS 0x18014000
#define RK2818_RTC_SIZE SZ_8K
#define RK2818_ADC_BASE 0xFF116000
#define RK2818_ADC_PHYS 0x18016000
#define RK2818_ADC_SIZE SZ_8K
#define RK2818_SCU_BASE 0xFF118000
#define RK2818_SCU_PHYS 0x18018000
#define RK2818_SCU_SIZE SZ_4K
#define RK2818_REGFILE_BASE 0xFF119000
#define RK2818_REGFILE_PHYS 0x18019000
#define RK2818_REGFILE_SIZE SZ_4K
#define RK2818_DSP_BASE 0xE0000000
#define RK2818_DSP_PHYS 0x80000000
#define RK2818_DSP_SIZE 0x00600000
#endif

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/* arch/arm/mach-rk2818/include/mach/system.h
*
* Copyright (C) 2010 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <mach/hardware.h>
void arch_idle(void);
static inline void arch_reset(char mode, const char *cmd)
{
for (;;) ; /* depends on IPC w/ other core */
}

21
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/* arch/arm/mach-rk2818/include/mach/timex.h
*
* Copyright (C) 2010 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __ASM_ARCH_RK2818_TIMEX_H
#define __ASM_ARCH_RK2818_TIMEX_H
#define CLOCK_TICK_RATE 50000000
#endif

36
arch/arm/mach-rk2818/include/mach/uncompress.h Normal file
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/* arch/arm/mach-rk2818/include/mach/uncompress.h
*
* Copyright (C) 2010 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __ASM_ARCH_RK2818_UNCOMPRESS_H
#include "hardware.h"
static void putc(int c)
{
}
static inline void flush(void)
{
}
static inline void arch_decomp_setup(void)
{
}
static inline void arch_decomp_wdog(void)
{
}
#endif

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arch/arm/mach-rk2818/include/mach/vmalloc.h Normal file
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/* arch/arm/mach-rk2818/include/mach/vmalloc.h
*
* Copyright (C) 2010 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __ASM_ARCH_RK2818_VMALLOC_H
#define __ASM_ARCH_RK2818_VMALLOC_H
#define VMALLOC_END (PAGE_OFFSET + 0x18000000)
#endif

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arch/arm/mach-rk2818/include/mach/vreg.h Normal file
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/* linux/include/asm-arm/arch-rk2818/vreg.h
*
* Copyright (C) 2010 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __ARCH_ARM_MACH_RK2818_VREG_H
#define __ARCH_ARM_MACH_RK2818_VREG_H
struct vreg;
struct vreg *vreg_get(struct device *dev, const char *id);
void vreg_put(struct vreg *vreg);
int vreg_enable(struct vreg *vreg);
void vreg_disable(struct vreg *vreg);
int vreg_set_level(struct vreg *vreg, unsigned mv);
#endif

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/* arch/arm/mach-rk2818/io.c
*
* Copyright (C) 2010 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <asm/page.h>
#include <mach/rk2818_iomap.h>
#include <asm/mach/map.h>
#include <mach/board.h>
#define RK2818_DEVICE(name) { \
.virtual = (unsigned long) RK2818_##name##_BASE, \
.pfn = __phys_to_pfn(RK2818_##name##_PHYS), \
.length = RK2818_##name##_SIZE, \
.type = MT_DEVICE_NONSHARED, \
}
static struct map_desc rk2818_io_desc[] __initdata = {
/*RK2818_DEVICE(VIC),
RK2818_DEVICE(CSR),
RK2818_DEVICE(GPT),
RK2818_DEVICE(DMOV),
RK2818_DEVICE(GPIO1),
RK2818_DEVICE(GPIO2),
RK2818_DEVICE(CLK_CTL),
{
.virtual = (unsigned long) RK2818_SHARED_RAM_BASE,
.pfn = __phys_to_pfn(RK2818_SHARED_RAM_PHYS),
.length = RK2818_SHARED_RAM_SIZE,
.type = MT_DEVICE,
},*/
};
void __init rk2818_map_common_io(void)
{
/* Make sure the peripheral register window is closed, since
* we will use PTE flags (TEX[1]=1,B=0,C=1) to determine which
* pages are peripheral interface or not.
*/
asm("mcr p15, 0, %0, c15, c2, 4" : : "r" (0));
iotable_init(rk2818_io_desc, ARRAY_SIZE(rk2818_io_desc));
}
void __iomem *
__rk2818_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
{
if (mtype == MT_DEVICE) {
/* The peripherals in the 88000000 - D0000000 range
* are only accessable by type MT_DEVICE_NONSHARED.
* Adjust mtype as necessary to make this "just work."
*/
if ((phys_addr >= 0x88000000) && (phys_addr < 0xD0000000))
mtype = MT_DEVICE_NONSHARED;
}
return __arm_ioremap(phys_addr, size, mtype);
}

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/* linux/arch/arm/mach-rk2818/irq.c
*
* Copyright (C) 2010 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/mm.h>
#include <linux/types.h>
//#include <asm/hardware.h>
//#include <asm/irq.h>
#include <asm/mach-types.h>
//#include <asm/setup.h>
//#include <asm/arch/typedef.h>
//#include <asm/arch/hardware.h>
#include <mach/irqs.h>
#include <mach/rk2818_iomap.h>
//#include "include/mach/irqs.h"
//#include "include/mach/rk2818_iomap.h"
//#include <asm/mach/arch.h>
#include <linux/irq.h>
//#include <asm/mach/map.h>
//#include <asm/hw_irq.h>
#include <asm/io.h>
#define which_irq_l(irq) (0x01u << (irq))
#define which_irq_h(irq) (0x01u << ((irq) & 0x1f))
#define write_irq_reg(addr, val) __raw_writel(val, addr+(RK2818_INTC_BASE))
#define read_irq_reg(addr) __raw_readl(addr+(RK2818_INTC_BASE))
#define set_irq_reg(addr, val) write_irq_reg(addr, ((val) | read_irq_reg(addr)))
#define clear_irq_reg(addr, val) write_irq_reg(addr, (~(val) & read_irq_reg(addr)))
u32 int_priority[NR_IRQS]={
/* priority name number */
0, //IRQ_DWDMA, 0 -- low
0, //IRQ_UHI, 1 -- USB Host Interface
0, //IRQ_NANDC, 2
0, //IRQ_LCDC, 3
0, //IRQ_SDMMC0, 4
0, //IRQ_VIP, 5
0, //IRQ_GPIO0, 6
0, //IRQ_GPIO1, 7
0, //IRQ_OTG, 8 -- USB OTG
0, //IRQ_ABTARMD, 9 -- Arbiter in ARMD BUS
0, //IRQ_ABTEXP, 10 -- Arbiter in EXP BUS
0, //IRQ_I2C0, 11
0, //IRQ_I2C1, 12
0, //IRQ_I2S, 13
0, //IRQ_SPIM, 14 -- SPI Master
0, //IRQ_SPIS, 15 -- SPI Slave
0, //IRQ_TIMER1, 16
0, //IRQ_TIMER2, 17
0, //IRQ_TIMER3, 18
0, //IRQ_UART0, 19
0, //IRQ_UART1, 20
0, //IRQ_WDT, 21
0, //IRQ_PWM0, 22
0, //IRQ_PWM1, 23
0, //IRQ_PWM2, 24
0, //IRQ_PWM3, 25
0, //IRQ_ADC, 26
0, //IRQ_RTC, 27
0, //IRQ_PIUSEM0, 28 -- PIU Semphore 0
0, //IRQ_PIUSEM1, 29
0, //IRQ_PIUSEM3, 30
0, //IRQ_PIUCMD, 31 -- PIU command/reply
0, //IRQ_XDMA, 32
0, //IRQ_SDMMC1, 33
0, //IRQ_DSPSEI, 34 -- DSP slave interface error interrupt
0, //IRQ_DSPSWI, 35 -- DSP interrupt by software set
0, //IRQ_SCU, 36
0, //IRQ_SWI, 37 -- Software Interrupt
0, //IRQ_DSPMEI, 38 -- DSP master interface error interrupt
0, //IRQ_DSPSAEI, 39 -- DSP system access error interrupt
0 //IRQ_MAXNUM 40 -- interrupt
};
static void rk2818_irq_ack(u32 irq)
{
//rk28 no irq ack
}
static void rk2818_irq_mask(u32 irq)
{
if (irq >= 32)
{
set_irq_reg(IRQ_REG_INTMASK_H, which_irq_h(irq));
}
else
{
set_irq_reg(IRQ_REG_INTMASK_L, which_irq_l(irq));
}
}
static void rk2818_irq_unmask(u32 irq)
{
if (irq >= 32)
{
clear_irq_reg(IRQ_REG_INTMASK_H, which_irq_h(irq));
}
else
{
clear_irq_reg(IRQ_REG_INTMASK_L, which_irq_l(irq));
}
}
static s32 rk2818_irq_wake(u32 irq, u32 value)
{
//rk28 no irq wake
return 0;
}
static struct irq_chip rk2818_irq_chip = {
.name = "rk2818_irq",
.ack = rk2818_irq_ack,
.mask = rk2818_irq_mask,
.unmask = rk2818_irq_unmask,
.set_wake = rk2818_irq_wake,
};
/*
* Initialize the AIC interrupt controller.
*/
void __init rk2818_init_irq(u32 priority[NR_IRQS])
{
u32 i;
write_irq_reg(IRQ_REG_INTEN_L, 0xffffffff);//enable irq interrupt
write_irq_reg(IRQ_REG_INTEN_H, 0xffffffff);
write_irq_reg(IRQ_REG_INTMASK_L, 0xffffffff); //mask all irq interrupt
write_irq_reg(IRQ_REG_INTMASK_H, 0xffffffff);
write_irq_reg(IRQ_REG_INTFORCE_L, 0);
write_irq_reg(IRQ_REG_INTFORCE_H, 0);
write_irq_reg(FIQ_REG_INTEN, 0x03); //enable fiq interrupt
write_irq_reg(FIQ_REG_INTMASK, 0x03); //mask fiq interrupt
write_irq_reg(IRQ_REG_PLEVEL, 0);
for (i = 0; i < NR_IRQS; i++) {
set_irq_chip(i, &rk2818_irq_chip);
set_irq_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID);//no probe and auto enable
}
}

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/* arch/arm/mach-rk2818/proc_comm.c
*
* Copyright (C) 2010 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/spinlock.h>
#include <mach/rk2818_iomap.h>
#include <mach/system.h>
#include "proc_comm.h"
//#define MSM_A2M_INT(n) (MSM_CSR_BASE + 0x400 + (n) * 4)
static inline void notify_other_proc_comm(void)
{
//writel(1, MSM_A2M_INT(6));
}
#define APP_COMMAND 0x00
#define APP_STATUS 0x04
#define APP_DATA1 0x08
#define APP_DATA2 0x0C
#define MDM_COMMAND 0x10
#define MDM_STATUS 0x14
#define MDM_DATA1 0x18
#define MDM_DATA2 0x1C
static DEFINE_SPINLOCK(proc_comm_lock);
/* The higher level SMD support will install this to
* provide a way to check for and handle modem restart.
*/
int (*rk2818_check_for_modem_crash)(void);
/* Poll for a state change, checking for possible
* modem crashes along the way (so we don't wait
* forever while the ARM9 is blowing up).
*
* Return an error in the event of a modem crash and
* restart so the msm_proc_comm() routine can restart
* the operation from the beginning.
*/
static int proc_comm_wait_for(void __iomem *addr, unsigned value)
{
for (;;) {
if (readl(addr) == value)
return 0;
if (rk2818_check_for_modem_crash)
if (rk2818_check_for_modem_crash())
return -EAGAIN;
}
}
int rk2818_proc_comm(unsigned cmd, unsigned *data1, unsigned *data2)
{
//void __iomem *base = MSM_SHARED_RAM_BASE;
unsigned long flags;
int ret=0;
spin_lock_irqsave(&proc_comm_lock, flags);
#if 0
for (;;) {
if (proc_comm_wait_for(base + MDM_STATUS, PCOM_READY))
continue;
writel(cmd, base + APP_COMMAND);
writel(data1 ? *data1 : 0, base + APP_DATA1);
writel(data2 ? *data2 : 0, base + APP_DATA2);
notify_other_proc_comm();
if (proc_comm_wait_for(base + APP_COMMAND, PCOM_CMD_DONE))
continue;
if (readl(base + APP_STATUS) != PCOM_CMD_FAIL) {
if (data1)
*data1 = readl(base + APP_DATA1);
if (data2)
*data2 = readl(base + APP_DATA2);
ret = 0;
} else {
ret = -EIO;
}
break;
}
writel(PCOM_CMD_IDLE, base + APP_COMMAND);
#endif
spin_unlock_irqrestore(&proc_comm_lock, flags);
return ret;
}

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/* arch/arm/mach-rk2818/proc_comm.h
*
* Copyright (c) 2010 ROCKCHIP
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef _ARCH_ARM_MACH_RK2818_PROC_COMM_H_
#define _ARCH_ARM_MACH_RK2818_PROC_COMM_H_
enum {
PCOM_CMD_IDLE = 0x0,
PCOM_CMD_DONE,
PCOM_RESET_APPS,
PCOM_RESET_CHIP,
PCOM_CONFIG_NAND_MPU,
PCOM_CONFIG_USB_CLKS,
PCOM_GET_POWER_ON_STATUS,
PCOM_GET_WAKE_UP_STATUS,
PCOM_GET_BATT_LEVEL,
PCOM_CHG_IS_CHARGING,
PCOM_POWER_DOWN,
PCOM_USB_PIN_CONFIG,
PCOM_USB_PIN_SEL,
PCOM_SET_RTC_ALARM,
PCOM_NV_READ,
PCOM_NV_WRITE,
PCOM_GET_UUID_HIGH,
PCOM_GET_UUID_LOW,
PCOM_GET_HW_ENTROPY,
PCOM_RPC_GPIO_TLMM_CONFIG_REMOTE,
PCOM_CLKCTL_RPC_ENABLE,
PCOM_CLKCTL_RPC_DISABLE,
PCOM_CLKCTL_RPC_RESET,
PCOM_CLKCTL_RPC_SET_FLAGS,
PCOM_CLKCTL_RPC_SET_RATE,
PCOM_CLKCTL_RPC_MIN_RATE,
PCOM_CLKCTL_RPC_MAX_RATE,
PCOM_CLKCTL_RPC_RATE,
PCOM_CLKCTL_RPC_PLL_REQUEST,
PCOM_CLKCTL_RPC_ENABLED,
PCOM_VREG_SWITCH,
PCOM_VREG_SET_LEVEL,
PCOM_GPIO_TLMM_CONFIG_GROUP,
PCOM_GPIO_TLMM_UNCONFIG_GROUP,
PCOM_NV_WRITE_BYTES_4_7,
PCOM_CONFIG_DISP,
PCOM_GET_FTM_BOOT_COUNT,
PCOM_RPC_GPIO_TLMM_CONFIG_EX,
PCOM_PM_MPP_CONFIG,
PCOM_GPIO_IN,
PCOM_GPIO_OUT,
PCOM_RESET_MODEM,
PCOM_RESET_CHIP_IMM,
PCOM_PM_VID_EN,
PCOM_VREG_PULLDOWN,
PCOM_NUM_CMDS,
};
enum {
PCOM_INVALID_STATUS = 0x0,
PCOM_READY,
PCOM_CMD_RUNNING,
PCOM_CMD_SUCCESS,
PCOM_CMD_FAIL,
};
/* List of VREGs that support the Pull Down Resistor setting. */
enum {
PM_VREG_PDOWN_MSMA_ID,
PM_VREG_PDOWN_MSMP_ID,
PM_VREG_PDOWN_MSME1_ID, /* Not supported in Panoramix */
PM_VREG_PDOWN_MSMC1_ID, /* Not supported in PM6620 */
PM_VREG_PDOWN_MSMC2_ID, /* Supported in PM7500 only */
PM_VREG_PDOWN_GP3_ID, /* Supported in PM7500 only */
PM_VREG_PDOWN_MSME2_ID, /* Supported in PM7500 and Panoramix only */
PM_VREG_PDOWN_GP4_ID, /* Supported in PM7500 only */
PM_VREG_PDOWN_GP1_ID, /* Supported in PM7500 only */
PM_VREG_PDOWN_TCXO_ID,
PM_VREG_PDOWN_PA_ID,
PM_VREG_PDOWN_RFTX_ID,
PM_VREG_PDOWN_RFRX1_ID,
PM_VREG_PDOWN_RFRX2_ID,
PM_VREG_PDOWN_SYNT_ID,
PM_VREG_PDOWN_WLAN_ID,
PM_VREG_PDOWN_USB_ID,
PM_VREG_PDOWN_MMC_ID,
PM_VREG_PDOWN_RUIM_ID,
PM_VREG_PDOWN_MSMC0_ID, /* Supported in PM6610 only */
PM_VREG_PDOWN_GP2_ID, /* Supported in PM7500 only */
PM_VREG_PDOWN_GP5_ID, /* Supported in PM7500 only */
PM_VREG_PDOWN_GP6_ID, /* Supported in PM7500 only */
PM_VREG_PDOWN_RF_ID,
PM_VREG_PDOWN_RF_VCO_ID,
PM_VREG_PDOWN_MPLL_ID,
PM_VREG_PDOWN_S2_ID,
PM_VREG_PDOWN_S3_ID,
PM_VREG_PDOWN_RFUBM_ID,
/* new for HAN */
PM_VREG_PDOWN_RF1_ID,
PM_VREG_PDOWN_RF2_ID,
PM_VREG_PDOWN_RFA_ID,
PM_VREG_PDOWN_CDC2_ID,
PM_VREG_PDOWN_RFTX2_ID,
PM_VREG_PDOWN_USIM_ID,
PM_VREG_PDOWN_USB2P6_ID,
PM_VREG_PDOWN_USB3P3_ID,
PM_VREG_PDOWN_INVALID_ID,
/* backward compatible enums only */
PM_VREG_PDOWN_CAM_ID = PM_VREG_PDOWN_GP1_ID,
PM_VREG_PDOWN_MDDI_ID = PM_VREG_PDOWN_GP2_ID,
PM_VREG_PDOWN_RUIM2_ID = PM_VREG_PDOWN_GP3_ID,
PM_VREG_PDOWN_AUX_ID = PM_VREG_PDOWN_GP4_ID,
PM_VREG_PDOWN_AUX2_ID = PM_VREG_PDOWN_GP5_ID,
PM_VREG_PDOWN_BT_ID = PM_VREG_PDOWN_GP6_ID,
PM_VREG_PDOWN_MSME_ID = PM_VREG_PDOWN_MSME1_ID,
PM_VREG_PDOWN_MSMC_ID = PM_VREG_PDOWN_MSMC1_ID,
PM_VREG_PDOWN_RFA1_ID = PM_VREG_PDOWN_RFRX2_ID,
PM_VREG_PDOWN_RFA2_ID = PM_VREG_PDOWN_RFTX2_ID,
PM_VREG_PDOWN_XO_ID = PM_VREG_PDOWN_TCXO_ID
};
/* gpio info for PCOM_RPC_GPIO_TLMM_CONFIG_EX */
#define GPIO_ENABLE 0
#define GPIO_DISABLE 1
#define GPIO_INPUT 0
#define GPIO_OUTPUT 1
#define GPIO_NO_PULL 0
#define GPIO_PULL_DOWN 1
#define GPIO_KEEPER 2
#define GPIO_PULL_UP 3
#define GPIO_2MA 0
#define GPIO_4MA 1
#define GPIO_6MA 2
#define GPIO_8MA 3
#define GPIO_10MA 4
#define GPIO_12MA 5
#define GPIO_14MA 6
#define GPIO_16MA 7
#define PCOM_GPIO_CFG(gpio, func, dir, pull, drvstr) \
((((gpio) & 0x3FF) << 4) | \
((func) & 0xf) | \
(((dir) & 0x1) << 14) | \
(((pull) & 0x3) << 15) | \
(((drvstr) & 0xF) << 17))
int rk2818_proc_comm(unsigned cmd, unsigned *data1, unsigned *data2);
#endif

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/* linux/arch/arm/mach-rk2818/timer.c
*
* Copyright (C) 2010 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/init.h>
#include <linux/time.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <asm/mach/time.h>
#include <mach/rk2818_iomap.h>
#define RK2818_TIMER1_BASE RK2818_TIMER_BASE
#define RK2818_TIMER2_BASE RK2818_TIMER_BASE + 0x14
#define RK2818_TIMER3_BASE RK2818_TIMER_BASE + 0x28
#define TIMER_LOAD_COUNT 0x0000
#define TIMER_CUR_VALUE 0x0004
#define TIMER_CONTROL_REG 0x0008
#define TIMER_EOI 0x000C
#define TIMER_INT_STATUS 0x0010
#define TIMER_MATCH_VAL 0x0000
#define TIMER_COUNT_VAL 0x0004
#define TIMER_ENABLE 0x0008
#define TIMER_ENABLE_CLR_ON_MATCH_EN 2
#define TIMER_ENABLE_EN 3
#define TIMER_CLEAR 0x000C
#define CSR_PROTECTION 0x0020
#define CSR_PROTECTION_EN 1
#define TIMER_HZ 24000000
#define timer_cycle (TIMER_HZ+HZ/2)/HZ
uint32_t tcount;
uint32_t mycycles = 0;
static int pit_cnt=0;
struct rk2818_clock {
struct clock_event_device clockevent;
struct clocksource clocksource;
struct irqaction irq;
uint32_t regbase;
uint32_t freq;
uint32_t shift;
};
static irqreturn_t rk2818_timer_interrupt(int irq, void *dev_id)
{
struct clock_event_device *evt = dev_id;
struct rk2818_clock *clock = container_of(evt, struct rk2818_clock, clockevent);
readl(clock->regbase + TIMER_EOI);
pit_cnt +=mycycles;
evt->event_handler(evt);
return IRQ_HANDLED;
}
static cycle_t rk2818_timer_read(void)
{
unsigned int elapsed;
unsigned int t;
t = readl(RK2818_TIMER3_BASE + TIMER_LOAD_COUNT);
elapsed = __raw_readl(RK2818_TIMER3_BASE + TIMER_CUR_VALUE);
elapsed = t - elapsed;
elapsed += pit_cnt;
return elapsed;
}
static int rk2818_timer_set_next_event(unsigned long cycles,
struct clock_event_device *evt)
{
struct rk2818_clock *clock = container_of(evt, struct rk2818_clock, clockevent);
writel(4, clock->regbase + TIMER_CONTROL_REG);
mycycles = cycles;
writel(cycles, clock->regbase + TIMER_LOAD_COUNT);
writel(TIMER_ENABLE_EN, clock->regbase + TIMER_CONTROL_REG);
return 0;
}
static void rk2818_timer_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
{
struct rk2818_clock *clock = container_of(evt, struct rk2818_clock, clockevent);
printk("%s::Enter--mode is %d\n",__FUNCTION__,mode);
switch (mode) {
case CLOCK_EVT_MODE_RESUME:
case CLOCK_EVT_MODE_PERIODIC:
break;
case CLOCK_EVT_MODE_ONESHOT:
readl(clock->regbase+TIMER_EOI);
writel((TIMER_HZ+ HZ/2) / HZ,clock->regbase+TIMER_LOAD_COUNT);
writel(TIMER_ENABLE_EN, clock->regbase + TIMER_CONTROL_REG);
break;
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
writel(4, clock->regbase + TIMER_CONTROL_REG);
break;
}
}
static struct rk2818_clock rk2818_clocks[] = {
{
.clockevent = {
.name = "timer",
.features = CLOCK_EVT_FEAT_ONESHOT,
.shift = 32,
.rating = 200,
.set_next_event = rk2818_timer_set_next_event,
.set_mode = rk2818_timer_set_mode,
},
.clocksource = {
.name = "timer",
.rating = 200,
.read = rk2818_timer_read,
.mask = CLOCKSOURCE_MASK(24),
.shift = 26,
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
},
.irq = {
.name = "timer",
.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_RISING,
.handler = rk2818_timer_interrupt,
.dev_id = &rk2818_clocks[0].clockevent,
.irq = IRQ_NR_TIMER3
},
.regbase = RK2818_TIMER3_BASE,
.freq = TIMER_HZ
}
};
static void __init rk2818_timer_init(void)
{
int i;
int res;
printk("%s [%d]\n",__FUNCTION__,__LINE__);
//rk2818_clock_init();
for (i = 0; i < ARRAY_SIZE(rk2818_clocks); i++) {
printk("%s::Enter %d\n",__FUNCTION__,i+1);
struct rk2818_clock *clock = &rk2818_clocks[i];
struct clock_event_device *ce = &clock->clockevent;
struct clocksource *cs = &clock->clocksource;
writel((TIMER_HZ+ HZ/2) / HZ,clock->regbase+TIMER_LOAD_COUNT);
writel(0x04, clock->regbase + TIMER_CONTROL_REG);
ce->mult = div_sc(clock->freq, NSEC_PER_SEC, ce->shift);
/* allow at least 10 seconds to notice that the timer wrapped */
ce->max_delta_ns =
clockevent_delta2ns(0xf0000000 >> clock->shift, ce);
/* 4 gets rounded down to 3 */
ce->min_delta_ns = clockevent_delta2ns(4, ce);
ce->cpumask = cpumask_of(0);
cs->mult = clocksource_hz2mult(clock->freq, cs->shift);
printk("mult is %x\n",cs->mult);
res = clocksource_register(cs);
if (res)
printk(KERN_ERR "rk2818_timer_init: clocksource_register "
"failed for %s\n", cs->name);
printk("%s::irq is %d\n",__FUNCTION__,clock->irq.irq);
res = setup_irq(clock->irq.irq, &clock->irq);
if (res)
printk(KERN_ERR "rk2818_timer_init: setup_irq "
"failed for %s\n", cs->name);
clockevents_register_device(ce);
}
}
struct sys_timer rk2818_timer = {
.init = rk2818_timer_init
};

142
arch/arm/mach-rk2818/vreg.c Normal file
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@@ -0,0 +1,142 @@
/* arch/arm/mach-rk2818/vreg.c
*
* Copyright (C) 2010 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/debugfs.h>
#include <mach/vreg.h>
#include "proc_comm.h"
struct vreg {
const char *name;
unsigned id;
};
#define VREG(_name, _id) { .name = _name, .id = _id, }
static struct vreg vregs[] = {
VREG("msma", 0),
VREG("msmp", 1),
VREG("msme1", 2),
VREG("msmc1", 3),
VREG("msmc2", 4),
VREG("gp3", 5),
VREG("msme2", 6),
VREG("gp4", 7),
VREG("gp1", 8),
VREG("tcxo", 9),
VREG("pa", 10),
VREG("rftx", 11),
VREG("rfrx1", 12),
VREG("rfrx2", 13),
VREG("synt", 14),
VREG("wlan", 15),
VREG("usb", 16),
VREG("boost", 17),
VREG("mmc", 18),
VREG("ruim", 19),
VREG("msmc0", 20),
VREG("gp2", 21),
VREG("gp5", 22),
VREG("gp6", 23),
VREG("rf", 24),
VREG("rf_vco", 26),
VREG("mpll", 27),
VREG("s2", 28),
VREG("s3", 29),
VREG("rfubm", 30),
VREG("ncp", 31),
};
struct vreg *vreg_get(struct device *dev, const char *id)
{
int n;
for (n = 0; n < ARRAY_SIZE(vregs); n++) {
if (!strcmp(vregs[n].name, id))
return vregs + n;
}
return 0;
}
void vreg_put(struct vreg *vreg)
{
}
int vreg_enable(struct vreg *vreg)
{
unsigned id = vreg->id;
unsigned enable = 1;
return rk2818_proc_comm(PCOM_VREG_SWITCH, &id, &enable);
}
void vreg_disable(struct vreg *vreg)
{
unsigned id = vreg->id;
unsigned enable = 0;
rk2818_proc_comm(PCOM_VREG_SWITCH, &id, &enable);
}
int vreg_set_level(struct vreg *vreg, unsigned mv)
{
unsigned id = vreg->id;
return rk2818_proc_comm(PCOM_VREG_SET_LEVEL, &id, &mv);
}
#if defined(CONFIG_DEBUG_FS)
static int vreg_debug_set(void *data, u64 val)
{
struct vreg *vreg = data;
switch (val) {
case 0:
vreg_disable(vreg);
break;
case 1:
vreg_enable(vreg);
break;
default:
vreg_set_level(vreg, val);
break;
}
return 0;
}
static int vreg_debug_get(void *data, u64 *val)
{
return -ENOSYS;
}
DEFINE_SIMPLE_ATTRIBUTE(vreg_fops, vreg_debug_get, vreg_debug_set, "%llu\n");
static int __init vreg_debug_init(void)
{
struct dentry *dent;
int n;
dent = debugfs_create_dir("vreg", 0);
if (IS_ERR(dent))
return 0;
for (n = 0; n < ARRAY_SIZE(vregs); n++)
(void) debugfs_create_file(vregs[n].name, 0644,
dent, vregs + n, &vreg_fops);
return 0;
}
device_initcall(vreg_debug_init);
#endif

2
arch/arm/tools/mach-types
View File

@@ -1608,7 +1608,7 @@ kb9263 MACH_KB9263 KB9263 1612
mt7108 MACH_MT7108 MT7108 1613
smtr2440 MACH_SMTR2440 SMTR2440 1614
manao MACH_MANAO MANAO 1615
cm_x300 MACH_CM_X300 CM_X300 1616
rk2818 MACH_RK2818 RK2818 1616
gulfstream_kp MACH_GULFSTREAM_KP GULFSTREAM_KP 1617
lanreadyfn522 MACH_LANREADYFN522 LANREADYFN522 1618
arma37 MACH_ARMA37 ARMA37 1619