Merge commit '0e7abd67ecee19952915ddbf39d4d85ada1966b5'

* commit '0e7abd67ecee19952915ddbf39d4d85ada1966b5':
  video: rockchip: rga3: "reg" debug log add iommu readback register printing
  video: rockchip: rga3: restore iommu status on soft-reset
  video: rockchip: rga3: modify the reset method to replace auto_rst on RK3576
  phy: rockchip: inno-usb2: Destroy chg_worker on probe failure
  ARM: dts: rockchip: add rv1126b-evb2-v12-aov-dual-cam.dts
  ethernet: stmmac: stmmac_uio: Fixes compilation errors
  arm64: dts: rockchip: add bt_port for wireless_bluetooth
  ARM: dts: rockchip: rk3506{g-demo-display-control,b-test2-v10}: Add "pmic-reset" for rk801
  misc: rk628: Fix compilation errors on 32-bit soc platforms.
  phy: rockchip: inno-usb2: Fix DEBUG_LOCKS_WARN_ON in chg work

Change-Id: I277f5b7050d74da8819633dfc5b1a0db059e3106
This commit is contained in:
Tao Huang
2025-07-23 18:49:59 +08:00
53 changed files with 271 additions and 102 deletions

View File

@@ -1196,6 +1196,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rv1126b-evb2-v10-sii9022-bt1120-to-hdmi.dtb \
rv1126b-evb2-v10-tb-400w-emmc.dtb \
rv1126b-evb2-v10-tb-400w-spi-nor.dtb \
rv1126b-evb2-v12-aov-dual-cam.dtb \
rv1126b-evb3-v10.dtb \
rv1126b-evb4-v10.dtb \
rv1126b-iotest-v10.dtb \

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@@ -20,8 +20,9 @@
interrupts = <RK_PC2 IRQ_TYPE_LEVEL_LOW>;
pwrctrl-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-names = "default", "pmic-reset";
pinctrl-0 = <&pmic_int>;
pinctrl-1 = <&soc_pwrctrl_reset>;
rockchip,system-power-controller;
wakeup-source;

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@@ -632,6 +632,10 @@
pmic_int: pmic-int {
rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
};
soc_pwrctrl_reset: soc-pwrctrl-reset {
rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_output_high>;
};
};
sdcard {

View File

@@ -526,6 +526,10 @@
pmic_int: pmic-int {
rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
};
soc_pwrctrl_reset: soc-pwrctrl-reset {
rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_output_high>;
};
};
psensor {

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@@ -0,0 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2025 Rockchip Electronics Co., Ltd.
*/
#include "arm64/rockchip/rv1126b-evb2-v10-aov-dual-cam.dts"

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@@ -164,6 +164,7 @@
wireless_bluetooth: wireless-bluetooth {
compatible = "bluetooth-platdata";
bt_port = "/dev/ttyS1";
clocks = <&rk809 1>;
clock-names = "ext_clock";
uart_rts_gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>;

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@@ -24,6 +24,7 @@
wireless_bluetooth: wireless-bluetooth {
compatible = "bluetooth-platdata";
bt_port = "/dev/ttyS2";
//wifi-bt-power-toggle;
uart_rts_gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "rts_gpio";

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@@ -22,6 +22,7 @@
wireless_bluetooth: wireless-bluetooth {
compatible = "bluetooth-platdata";
bt_port = "/dev/ttyS2";
//wifi-bt-power-toggle;
uart_rts_gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "rts_gpio";

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@@ -52,6 +52,7 @@
wireless_bluetooth: wireless-bluetooth {
compatible = "bluetooth-platdata";
bt_port = "/dev/ttyS2";
//wifi-bt-power-toggle;
uart_rts_gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "rts_gpio";

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@@ -24,6 +24,7 @@
wireless_bluetooth: wireless-bluetooth {
compatible = "bluetooth-platdata";
bt_port = "/dev/ttyS2";
//wifi-bt-power-toggle;
uart_rts_gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "rts_gpio";

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@@ -53,6 +53,7 @@
wireless_bluetooth: wireless-bluetooth {
compatible = "bluetooth-platdata";
bt_port = "/dev/ttyS2";
//wifi-bt-power-toggle;
uart_rts_gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "rts_gpio";

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@@ -55,6 +55,7 @@
wireless_bluetooth: wireless-bluetooth {
compatible = "bluetooth-platdata";
bt_port = "/dev/ttyS2";
uart_rts_gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "rts_gpio";
pinctrl-0 = <&uart2m0_rtsn>;

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@@ -438,6 +438,7 @@
};
&wireless_bluetooth {
bt_port = "/dev/ttyS1";
uart_rts_gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "rts_gpio";
pinctrl-0 = <&uart1m1_rtsn>;

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@@ -577,6 +577,7 @@
&wireless_bluetooth {
compatible = "bluetooth-platdata";
bt_port = "/dev/ttyS1";
clocks = <&rk809 1>;
clock-names = "ext_clock";
//wifi-bt-power-toggle;

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@@ -506,6 +506,7 @@
&wireless_bluetooth {
compatible = "bluetooth-platdata";
bt_port = "/dev/ttyS1";
clocks = <&rk809 1>;
clock-names = "ext_clock";
//wifi-bt-power-toggle;

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@@ -282,6 +282,7 @@
&wireless_bluetooth {
uart_rts_gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>;
bt_port = "/dev/ttyS1";
pinctrl-names = "default", "rts_gpio";
pinctrl-0 = <&uart1m1_rtsn>;
pinctrl-1 = <&uart1_gpios>;

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@@ -609,6 +609,7 @@
&wireless_bluetooth {
compatible = "bluetooth-platdata";
bt_port = "/dev/ttyS1";
clocks = <&rk809 1>;
clock-names = "ext_clock";
//wifi-bt-power-toggle;

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@@ -634,6 +634,7 @@
&wireless_bluetooth {
compatible = "bluetooth-platdata";
bt_port = "/dev/ttyS1";
clocks = <&rk809 1>;
clock-names = "ext_clock";
//wifi-bt-power-toggle;

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@@ -348,6 +348,7 @@
wireless_bluetooth: wireless-bluetooth {
compatible = "bluetooth-platdata";
bt_port = "/dev/ttyS8";
clocks = <&rk809 1>;
clock-names = "ext_clock";
//wifi-bt-power-toggle;

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@@ -497,6 +497,7 @@
&wireless_bluetooth {
compatible = "bluetooth-platdata";
bt_port = "/dev/ttyS8";
clocks = <&rk809 1>;
clock-names = "ext_clock";
//wifi-bt-power-toggle;

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@@ -587,6 +587,7 @@
&wireless_bluetooth {
compatible = "bluetooth-platdata";
bt_port = "/dev/ttyS1";
clocks = <&pmucru CLK_RTC_32K>;
clock-names = "ext_clock";
//wifi-bt-power-toggle;

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@@ -556,6 +556,7 @@
&wireless_bluetooth {
compatible = "bluetooth-platdata";
bt_port = "/dev/ttyS8";
clocks = <&rk809 1>;
clock-names = "ext_clock";
//wifi-bt-power-toggle;

View File

@@ -444,6 +444,7 @@
&wireless_bluetooth {
compatible = "bluetooth-platdata";
bt_port = "/dev/ttyS1";
clocks = <&pmucru CLK_RTC_32K>;
clock-names = "ext_clock";
//wifi-bt-power-toggle;

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@@ -367,6 +367,7 @@
wireless_bluetooth: wireless-bluetooth {
compatible = "bluetooth-platdata";
bt_port = "/dev/ttyS8";
clocks = <&rk809 1>;
clock-names = "ext_clock";
//wifi-bt-power-toggle;

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@@ -194,6 +194,7 @@
wireless_bluetooth: wireless-bluetooth {
compatible = "bluetooth-platdata";
bt_port = "/dev/ttyS4";
clocks = <&hym8563>;
clock-names = "ext_clock";
uart_rts_gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;

View File

@@ -208,6 +208,7 @@
wireless_bluetooth: wireless-bluetooth {
compatible = "bluetooth-platdata";
bt_port = "/dev/ttyS4";
clocks = <&hym8563>;
clock-names = "ext_clock";
uart_rts_gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;

View File

@@ -207,6 +207,7 @@
wireless_bluetooth: wireless-bluetooth {
compatible = "bluetooth-platdata";
bt_port = "/dev/ttyS4";
uart_rts_gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "rts_gpio";
pinctrl-0 = <&uart4m1_rtsn>;

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@@ -254,6 +254,7 @@
wireless_bluetooth: wireless-bluetooth {
compatible = "bluetooth-platdata";
bt_port = "/dev/ttyS4";
uart_rts_gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "rts_gpio";
pinctrl-0 = <&uart4m1_rtsn>;

View File

@@ -173,6 +173,7 @@
wireless_bluetooth: wireless-bluetooth {
compatible = "bluetooth-platdata";
bt_port = "/dev/ttyS4";
uart_rts_gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "rts_gpio";
pinctrl-0 = <&uart4m1_rtsn>;

View File

@@ -207,6 +207,7 @@
wireless_bluetooth: wireless-bluetooth {
compatible = "bluetooth-platdata";
bt_port = "/dev/ttyS4";
uart_rts_gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "rts_gpio";
pinctrl-0 = <&uart4m1_rtsn>;

View File

@@ -261,6 +261,7 @@
wireless_bluetooth: wireless-bluetooth {
compatible = "bluetooth-platdata";
bt_port = "/dev/ttyS4";
uart_rts_gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "rts_gpio";
pinctrl-0 = <&uart4m1_rtsn>;

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@@ -214,6 +214,7 @@
wireless_bluetooth: wireless-bluetooth {
compatible = "bluetooth-platdata";
bt_port = "/dev/ttyS8";
clocks = <&hym8563>;
clock-names = "ext_clock";
uart_rts_gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>;

View File

@@ -171,6 +171,7 @@
wireless_bluetooth: wireless-bluetooth {
compatible = "bluetooth-platdata";
bt_port = "/dev/ttyS9";
clocks = <&hym8563>;
clock-names = "ext_clock";
uart_rts_gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>;

View File

@@ -175,6 +175,7 @@
wireless_bluetooth: wireless-bluetooth {
compatible = "bluetooth-platdata";
bt_port = "/dev/ttyS8";
clocks = <&hym8563>;
clock-names = "ext_clock";
uart_rts_gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>;

View File

@@ -238,6 +238,7 @@
wireless_bluetooth: wireless-bluetooth {
compatible = "bluetooth-platdata";
bt_port = "/dev/ttyS7";
clocks = <&hym8563>;
clock-names = "ext_clock";
uart_rts_gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>;

View File

@@ -250,6 +250,7 @@
wireless_bluetooth: wireless-bluetooth {
compatible = "bluetooth-platdata";
bt_port = "/dev/ttyS9";
clocks = <&hym8563>;
clock-names = "ext_clock";
uart_rts_gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>;

View File

@@ -96,6 +96,7 @@
wireless_bluetooth: wireless-bluetooth {
compatible = "bluetooth-platdata";
bt_port = "/dev/ttyS9";
clocks = <&hym8563>;
clock-names = "ext_clock";
uart_rts_gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>;

View File

@@ -108,6 +108,7 @@
wireless_bluetooth: wireless-bluetooth {
compatible = "bluetooth-platdata";
bt_port = "/dev/ttyS9";
clocks = <&hym8563>;
clock-names = "ext_clock";
uart_rts_gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>;

View File

@@ -494,6 +494,7 @@
wireless_bluetooth: wireless-bluetooth {
compatible = "bluetooth-platdata";
bt_port = "/dev/ttyS7";
clocks = <&hym8563>;
clock-names = "ext_clock";
uart_rts_gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>;

View File

@@ -178,6 +178,7 @@
wireless_bluetooth: wireless-bluetooth {
compatible = "bluetooth-platdata";
bt_port = "/dev/ttyS9";
clocks = <&hym8563>;
clock-names = "ext_clock";
uart_rts_gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>;

View File

@@ -216,6 +216,7 @@
wireless_bluetooth: wireless-bluetooth {
compatible = "bluetooth-platdata";
bt_port = "/dev/ttyS8";
clocks = <&hym8563>;
clock-names = "ext_clock";
uart_rts_gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>;

View File

@@ -199,6 +199,7 @@
wireless_bluetooth: wireless-bluetooth {
compatible = "bluetooth-platdata";
bt_port = "/dev/ttyS8";
clocks = <&hym8563>;
clock-names = "ext_clock";
uart_rts_gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>;

View File

@@ -180,6 +180,7 @@
wireless_bluetooth: wireless-bluetooth {
compatible = "bluetooth-platdata";
bt_port = "/dev/ttyS8";
clocks = <&hym8563>;
clock-names = "ext_clock";
uart_rts_gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>;

View File

@@ -296,6 +296,7 @@
wireless_bluetooth: wireless-bluetooth {
compatible = "bluetooth-platdata";
bt_port = "/dev/ttyS7";
clocks = <&hym8563>;
clock-names = "ext_clock";
uart_rts_gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>;

View File

@@ -293,6 +293,7 @@
wireless_bluetooth: wireless-bluetooth {
compatible = "bluetooth-platdata";
bt_port = "/dev/ttyS7";
clocks = <&hym8563>;
clock-names = "ext_clock";
uart_rts_gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>;

View File

@@ -994,7 +994,7 @@ static void rk628_show_resolution(struct seq_file *s)
src_vtotal = src_mode->vtotal;
/* get fps */
fps = src_dclk * 1000 / (src_htotal * src_vtotal);
fps = DIV_ROUND_CLOSEST_ULL(src_dclk * 1000, src_htotal * src_vtotal);
clk_rx_read = rk628_cru_clk_get_rate(rk628, CGU_CLK_RX_READ) / 1000;
@@ -1058,7 +1058,7 @@ static void rk628f_show_rgbrx_resolution(struct seq_file *s)
src_vtotal = val & 0xffff;
/* get fps */
fps = src_dclk * 1000 / (src_htotal * src_vtotal);
fps = DIV_ROUND_CLOSEST_ULL(src_dclk * 1000, src_htotal * src_vtotal);
clk_rx_read = rk628_cru_clk_get_rate(rk628, CGU_CLK_RX_READ) / 1000;
@@ -1117,7 +1117,7 @@ static void rk628_show_output_resolution(struct seq_file *s)
dsp_vact_end = val & 0xfff;
/* get fps */
fps = sclk_vop * 1000 / (dsp_vtotal * dsp_htotal);
fps = DIV_ROUND_CLOSEST_ULL(sclk_vop * 1000, (dsp_vtotal * dsp_htotal));
bus_format_s = rk628_get_output_bus_format_name(rk628);

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@@ -115,15 +115,15 @@ static void uio_free_dma_rx_desc_resources(struct stmmac_priv *priv)
/* Free RX queue resources */
for (queue = 0; queue < rx_count; queue++) {
struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue];
/* Free DMA regions of consistent memory previously allocated */
if (!priv->extend_desc)
dma_free_coherent(priv->device, priv->dma_rx_size *
dma_free_coherent(priv->device, priv->dma_conf.dma_rx_size *
sizeof(struct dma_desc),
rx_q->dma_rx, rx_q->dma_rx_phy);
else
dma_free_coherent(priv->device, priv->dma_rx_size *
dma_free_coherent(priv->device, priv->dma_conf.dma_rx_size *
sizeof(struct dma_extended_desc),
rx_q->dma_erx, rx_q->dma_rx_phy);
}
@@ -140,7 +140,7 @@ static void uio_free_dma_tx_desc_resources(struct stmmac_priv *priv)
/* Free TX queue resources */
for (queue = 0; queue < tx_count; queue++) {
struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
size_t size;
void *addr;
@@ -155,7 +155,7 @@ static void uio_free_dma_tx_desc_resources(struct stmmac_priv *priv)
addr = tx_q->dma_tx;
}
size *= priv->dma_tx_size;
size *= priv->dma_conf.dma_tx_size;
dma_free_coherent(priv->device, size, addr, tx_q->dma_tx_phy);
}
@@ -177,11 +177,11 @@ static int uio_alloc_dma_rx_desc_resources(struct stmmac_priv *priv)
/* RX queues buffers and DMA */
for (queue = 0; queue < rx_count; queue++) {
struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue];
if (priv->extend_desc) {
rx_q->dma_erx = dma_alloc_coherent(priv->device,
priv->dma_rx_size *
priv->dma_conf.dma_rx_size *
sizeof(struct dma_extended_desc),
&rx_q->dma_rx_phy,
GFP_KERNEL);
@@ -189,7 +189,7 @@ static int uio_alloc_dma_rx_desc_resources(struct stmmac_priv *priv)
goto err_dma;
} else {
rx_q->dma_rx = dma_alloc_coherent(priv->device,
priv->dma_rx_size *
priv->dma_conf.dma_rx_size *
sizeof(struct dma_desc),
&rx_q->dma_rx_phy,
GFP_KERNEL);
@@ -222,7 +222,7 @@ static int uio_alloc_dma_tx_desc_resources(struct stmmac_priv *priv)
/* TX queues buffers and DMA */
for (queue = 0; queue < tx_count; queue++) {
struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
size_t size;
void *addr;
@@ -236,7 +236,7 @@ static int uio_alloc_dma_tx_desc_resources(struct stmmac_priv *priv)
else
size = sizeof(struct dma_desc);
size *= priv->dma_tx_size;
size *= priv->dma_conf.dma_tx_size;
addr = dma_alloc_coherent(priv->device, size,
&tx_q->dma_tx_phy, GFP_KERNEL);
@@ -382,13 +382,13 @@ static int rockchip_gmac_uio_init_dma_engine(struct stmmac_priv *priv)
/* DMA RX Channel Configuration */
for (chan = 0; chan < rx_channels_count; chan++) {
rx_q = &priv->rx_queue[chan];
rx_q = &priv->dma_conf.rx_queue[chan];
stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
rx_q->dma_rx_phy, chan);
rx_q->rx_tail_addr = rx_q->dma_rx_phy +
(priv->dma_rx_size *
(priv->dma_conf.dma_rx_size *
sizeof(struct dma_desc));
stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
rx_q->rx_tail_addr, chan);
@@ -396,7 +396,7 @@ static int rockchip_gmac_uio_init_dma_engine(struct stmmac_priv *priv)
/* DMA TX Channel Configuration */
for (chan = 0; chan < tx_channels_count; chan++) {
tx_q = &priv->tx_queue[chan];
tx_q = &priv->dma_conf.tx_queue[chan];
stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
tx_q->dma_tx_phy, chan);
@@ -418,12 +418,12 @@ static void uio_set_rings_length(struct stmmac_priv *priv)
/* set TX ring length */
for (chan = 0; chan < tx_channels_count; chan++)
stmmac_set_tx_ring_len(priv, priv->ioaddr,
(priv->dma_tx_size - 1), chan);
(priv->dma_conf.dma_tx_size - 1), chan);
/* set RX ring length */
for (chan = 0; chan < rx_channels_count; chan++)
stmmac_set_rx_ring_len(priv, priv->ioaddr,
(priv->dma_rx_size - 1), chan);
(priv->dma_conf.dma_rx_size - 1), chan);
}
/**
@@ -634,7 +634,8 @@ static void uio_safety_feat_configuration(struct stmmac_priv *priv)
{
if (priv->dma_cap.asp) {
netdev_info(priv->dev, "Enabling Safety Features\n");
stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp);
stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp,
priv->plat->safety_feat_cfg);
} else {
netdev_info(priv->dev, "No Safety Features support found\n");
}
@@ -690,7 +691,7 @@ static void uio_dma_operation_mode(struct stmmac_priv *priv)
stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan,
rxfifosz, qmode);
stmmac_set_dma_bfsize(priv, priv->ioaddr, priv->dma_buf_sz,
stmmac_set_dma_bfsize(priv, priv->ioaddr, priv->dma_conf.dma_buf_sz,
chan);
}
@@ -828,17 +829,17 @@ static int uio_open(struct net_device *dev)
bfsize = 0;
if (bfsize < BUF_SIZE_16KiB)
bfsize = uio_set_bfsize(dev->mtu, priv->dma_buf_sz);
bfsize = uio_set_bfsize(dev->mtu, priv->dma_conf.dma_buf_sz);
priv->dma_buf_sz = bfsize;
priv->dma_conf.dma_buf_sz = bfsize;
buf_sz = bfsize;
priv->rx_copybreak = STMMAC_RX_COPYBREAK;
if (!priv->dma_tx_size)
priv->dma_tx_size = DMA_DEFAULT_TX_SIZE;
if (!priv->dma_rx_size)
priv->dma_rx_size = DMA_DEFAULT_RX_SIZE;
if (!priv->dma_conf.dma_tx_size)
priv->dma_conf.dma_tx_size = DMA_DEFAULT_TX_SIZE;
if (!priv->dma_conf.dma_rx_size)
priv->dma_conf.dma_rx_size = DMA_DEFAULT_RX_SIZE;
ret = uio_alloc_dma_desc_resources(priv);
if (ret < 0) {
@@ -963,13 +964,13 @@ static int rockchip_gmac_uio_probe(struct platform_device *pdev)
uio->mem[0].memtype = UIO_MEM_PHYS;
uio->mem[1].name = "eth_rx_bd";
uio->mem[1].addr = priv->rx_queue[0].dma_rx_phy;
uio->mem[1].size = priv->dma_rx_size * sizeof(struct dma_desc);
uio->mem[1].addr = priv->dma_conf.rx_queue[0].dma_rx_phy;
uio->mem[1].size = priv->dma_conf.dma_rx_size * sizeof(struct dma_desc);
uio->mem[1].memtype = UIO_MEM_PHYS;
uio->mem[2].name = "eth_tx_bd";
uio->mem[2].addr = priv->tx_queue[0].dma_tx_phy;
uio->mem[2].size = priv->dma_tx_size * sizeof(struct dma_desc);
uio->mem[2].addr = priv->dma_conf.tx_queue[0].dma_tx_phy;
uio->mem[2].size = priv->dma_conf.dma_tx_size * sizeof(struct dma_desc);
uio->mem[2].memtype = UIO_MEM_PHYS;
uio->open = rockchip_gmac_uio_open;

View File

@@ -267,10 +267,11 @@ struct rockchip_usb2phy_cfg {
* @otg_mux_irq: IRQ number which multiplex otg-id/otg-bvalid/linestate
* irqs to one irq in otg-port.
* @mutex: for register updating in sm_work.
* @chg_work: charge detect work.
* @bypass_uart_work: usb bypass uart work.
* @otg_sm_work: OTG state machine work.
* @sm_work: HOST state machine work.
* @chg_work: charge detect kthread work.
* @chg_worker: charge detect kthread worker.
* @vbus: vbus regulator supply on few rockchip boards.
* @sw: orientation switch, communicate with TCPM (Type-C Port Manager).
* @port_cfg: port register configuration, assigned by driver data.
@@ -304,9 +305,10 @@ struct rockchip_usb2phy_port {
int otg_mux_irq;
struct mutex mutex;
struct delayed_work bypass_uart_work;
struct delayed_work chg_work;
struct delayed_work otg_sm_work;
struct delayed_work sm_work;
struct kthread_work chg_work;
struct kthread_worker *chg_worker;
struct regulator *vbus;
struct typec_switch_dev *sw;
const struct rockchip_usb2phy_port_cfg *port_cfg;
@@ -1306,7 +1308,7 @@ static void rockchip_usb2phy_otg_sm_work(struct work_struct *work)
switch (rphy->chg_state) {
case USB_CHG_STATE_UNDEFINED:
mutex_unlock(&rport->mutex);
schedule_delayed_work(&rport->chg_work, 0);
kthread_queue_work(rport->chg_worker, &rport->chg_work);
return;
case USB_CHG_STATE_DETECTED:
switch (rphy->chg_type) {
@@ -1472,46 +1474,17 @@ static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy,
#define CHG_DCD_MAX_RETRIES 6
#define CHG_PRIMARY_DET_TIME (40 * HZ / 1000)
#define CHG_SECONDARY_DET_TIME (40 * HZ / 1000)
static void rockchip_chg_detect_work(struct work_struct *work)
static void rockchip_run_chg_detect_machine(struct rockchip_usb2phy_port *rport)
{
struct rockchip_usb2phy_port *rport =
container_of(work, struct rockchip_usb2phy_port, chg_work.work);
struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
struct regmap *base = get_reg_base(rphy);
const struct usb2phy_reg *phy_sus_reg;
bool is_dcd, tmout, vout;
unsigned long delay;
unsigned int mask;
int ret;
dev_dbg(&rport->phy->dev, "chg detection work state = %d\n",
rphy->chg_state);
/*
* The conditions for charger detection:
* 1. Set the PHY in normal mode to keep the UTMI_CLK on.
* 2. Set the utmi_opmode in non-driving mode.
* 3. Set the utmi_xcvrselect to FS speed.
* 4. Set the utmi_termselect to FS speed.
* 5. Enable the DP/DM pulldown resistor.
*/
switch (rphy->chg_state) {
case USB_CHG_STATE_UNDEFINED:
mutex_lock(&rport->mutex);
/* Store the PHY current suspend configuration */
phy_sus_reg = &rport->port_cfg->phy_sus;
ret = regmap_read(base, phy_sus_reg->offset,
&rphy->phy_sus_cfg);
if (ret) {
dev_err(&rport->phy->dev,
"Fail to read phy_sus reg offset 0x%x, ret %d\n",
phy_sus_reg->offset, ret);
mutex_unlock(&rport->mutex);
return;
}
/* Set the PHY in charger detection mode */
property_enable(base, &rphy->phy_cfg->chg_det.chg_mode, true);
/* Start DCD processing stage 1 */
rockchip_chg_enable_dcd(rphy, true);
rphy->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
@@ -1585,37 +1558,75 @@ static void rockchip_chg_detect_work(struct work_struct *work)
fallthrough;
case USB_CHG_STATE_SECONDARY_DONE:
rphy->chg_state = USB_CHG_STATE_DETECTED;
fallthrough;
case USB_CHG_STATE_DETECTED:
if (rphy->phy_cfg->chg_det.chg_mode.offset !=
rport->port_cfg->phy_sus.offset)
property_enable(base, &rphy->phy_cfg->chg_det.chg_mode, false);
/* Restore the PHY suspend configuration */
phy_sus_reg = &rport->port_cfg->phy_sus;
mask = GENMASK(phy_sus_reg->bitend, phy_sus_reg->bitstart);
ret = regmap_write(base, phy_sus_reg->offset,
(rphy->phy_sus_cfg | (mask << BIT_WRITEABLE_SHIFT)));
if (ret)
dev_err(&rport->phy->dev,
"Fail to set phy_sus reg offset 0x%x, ret %d\n",
phy_sus_reg->offset, ret);
mutex_unlock(&rport->mutex);
rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
dev_dbg(&rport->phy->dev, "charger = %s\n",
chg_to_string(rphy->chg_type));
return;
default:
rphy->chg_state = USB_CHG_STATE_DETECTED;
rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
return;
}
if (delay)
msleep(jiffies_to_msecs(delay));
}
static void rockchip_chg_detect_work(struct kthread_work *work)
{
struct rockchip_usb2phy_port *rport =
container_of(work, struct rockchip_usb2phy_port, chg_work);
struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
struct regmap *base = get_reg_base(rphy);
const struct usb2phy_reg *phy_sus_reg;
unsigned int mask;
int ret;
mutex_lock(&rport->mutex);
/* Store the PHY current suspend configuration */
phy_sus_reg = &rport->port_cfg->phy_sus;
ret = regmap_read(base, phy_sus_reg->offset, &rphy->phy_sus_cfg);
if (ret) {
dev_err(&rport->phy->dev,
"Fail to read phy_sus reg offset 0x%x, ret %d\n",
phy_sus_reg->offset, ret);
mutex_unlock(&rport->mutex);
return;
}
/*
* Hold the mutex lock during the whole charger
* detection stage, and release it after detect
* the charger type.
/* Set the PHY in charger detection mode.
* The conditions for charger detection:
* 1. Set the PHY in normal mode to keep the UTMI_CLK on.
* 2. Set the utmi_opmode in non-driving mode.
* 3. Set the utmi_xcvrselect to FS speed.
* 4. Set the utmi_termselect to FS speed.
* 5. Enable the DP/DM pulldown resistor.
*/
schedule_delayed_work(&rport->chg_work, delay);
property_enable(base, &rphy->phy_cfg->chg_det.chg_mode, true);
do {
rockchip_run_chg_detect_machine(rport);
} while (rphy->chg_state != USB_CHG_STATE_UNDEFINED &&
rphy->chg_state != USB_CHG_STATE_DETECTED);
dev_info(&rport->phy->dev, "charger = %s\n", chg_to_string(rphy->chg_type));
/* Disable charger detection mode */
if (rphy->phy_cfg->chg_det.chg_mode.offset != rport->port_cfg->phy_sus.offset)
property_enable(base, &rphy->phy_cfg->chg_det.chg_mode, false);
/* Restore the PHY suspend configuration */
phy_sus_reg = &rport->port_cfg->phy_sus;
mask = GENMASK(phy_sus_reg->bitend, phy_sus_reg->bitstart);
ret = regmap_write(base, phy_sus_reg->offset,
(rphy->phy_sus_cfg | (mask << BIT_WRITEABLE_SHIFT)));
if (ret)
dev_err(&rport->phy->dev,
"Fail to set phy_sus reg offset 0x%x, ret %d\n",
phy_sus_reg->offset, ret);
mutex_unlock(&rport->mutex);
if (rphy->chg_state == USB_CHG_STATE_DETECTED)
rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
}
/*
@@ -2382,7 +2393,6 @@ static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy,
INIT_DELAYED_WORK(&rport->bypass_uart_work,
rockchip_usb_bypass_uart_work);
INIT_DELAYED_WORK(&rport->chg_work, rockchip_chg_detect_work);
INIT_DELAYED_WORK(&rport->otg_sm_work, rockchip_usb2phy_otg_sm_work);
if (!IS_ERR(rphy->edev)) {
@@ -2396,6 +2406,12 @@ static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy,
}
}
rport->chg_worker = kthread_create_worker(0, "usbchg-worker-%d",
rport->phy->id);
if (IS_ERR(rport->chg_worker))
return PTR_ERR(rport->chg_worker);
kthread_init_work(&rport->chg_work, rockchip_chg_detect_work);
out:
/*
* Let us put phy-port into suspend mode here for saving power
@@ -2618,6 +2634,16 @@ next_child:
return 0;
put_child:
for (index = 0; index < rphy->phy_cfg->num_ports; index++) {
struct rockchip_usb2phy_port *rport = &rphy->ports[index];
if (!rport->phy)
continue;
if (rport->port_id == USB2PHY_PORT_OTG && !IS_ERR_OR_NULL(rport->chg_worker))
kthread_destroy_worker(rport->chg_worker);
}
of_node_put(child_np);
disable_clks:
pm_runtime_put_sync(dev);
@@ -2626,6 +2652,31 @@ disable_clks:
return ret;
}
static int rockchip_usb2phy_remove(struct platform_device *pdev)
{
struct rockchip_usb2phy *rphy = platform_get_drvdata(pdev);
struct rockchip_usb2phy_port *rport;
unsigned int index;
for (index = 0; index < rphy->phy_cfg->num_ports; index++) {
rport = &rphy->ports[index];
if (!rport->phy)
continue;
if (rport->port_id == USB2PHY_PORT_HOST) {
cancel_delayed_work_sync(&rport->sm_work);
} else if (rport->port_id == USB2PHY_PORT_OTG) {
if (rport->chg_worker)
kthread_destroy_worker(rport->chg_worker);
if (rport->otg_sm_work.work.func)
cancel_delayed_work_sync(&rport->otg_sm_work);
}
}
return 0;
}
static int __maybe_unused
rockchip_usb2phy_low_power_enable(struct rockchip_usb2phy *rphy,
struct rockchip_usb2phy_port *rport,
@@ -4802,6 +4853,7 @@ MODULE_DEVICE_TABLE(of, rockchip_usb2phy_dt_match);
static struct platform_driver rockchip_usb2phy_driver = {
.probe = rockchip_usb2phy_probe,
.remove = rockchip_usb2phy_remove,
.driver = {
.name = "rockchip-usb2phy",
.pm = ROCKCHIP_USB2PHY_DEV_PM,

View File

@@ -8,6 +8,7 @@
#define RGA2_CSC_REG_BASE 0x060
#define RGA2_OTHER_REG_BASE 0x090
#define RGA2_CMD_REG_BASE 0x100
#define RGA2_IOMMU_REG_BASE 0xf00
/* sys reg */
#define RGA2_SYS_CTRL 0x000

View File

@@ -6,6 +6,7 @@
#define RGA3_SYS_REG_BASE 0x000
#define RGA3_CMD_REG_BASE 0x100
#define RGA3_IOMMU_REG_BASE 0xf00
/* sys reg */
#define RGA3_SYS_CTRL 0x000

View File

@@ -88,7 +88,7 @@
#define DRIVER_MAJOR_VERISON 1
#define DRIVER_MINOR_VERSION 3
#define DRIVER_REVISION_VERSION 9
#define DRIVER_REVISION_VERSION 10
#define DRIVER_PATCH_VERSION
#define DRIVER_VERSION (STR(DRIVER_MAJOR_VERISON) "." STR(DRIVER_MINOR_VERSION) \

View File

@@ -2695,10 +2695,13 @@ static void rga2_soft_reset(struct rga_scheduler_t *scheduler)
{
u32 i;
u32 reg;
u32 iommu_dte_addr = 0;
u32 iommu_dte_addr = 0, iommu_int_mask = 0, iommu_auto_gate = 0;
if (scheduler->data->mmu == RGA_IOMMU)
if (scheduler->data->mmu == RGA_IOMMU) {
iommu_dte_addr = rga_read(RGA_IOMMU_DTE_ADDR, scheduler);
iommu_int_mask = rga_read(RGA_IOMMU_INT_MASK, scheduler);
iommu_auto_gate = rga_read(RGA_IOMMU_AUTO_GATING, scheduler);
}
rga_write(m_RGA2_SYS_CTRL_ACLK_SRESET_P | m_RGA2_SYS_CTRL_CCLK_SRESET_P |
m_RGA2_SYS_CTRL_RST_PROTECT_P,
@@ -2716,6 +2719,11 @@ static void rga2_soft_reset(struct rga_scheduler_t *scheduler)
if (scheduler->data->mmu == RGA_IOMMU) {
rga_write(iommu_dte_addr, RGA_IOMMU_DTE_ADDR, scheduler);
rga_write(RGA_IOMMU_CMD_ZAP_CACHE, RGA_IOMMU_COMMAND, scheduler);
rga_write(iommu_int_mask, RGA_IOMMU_INT_MASK, scheduler);
rga_write(iommu_auto_gate, RGA_IOMMU_AUTO_GATING, scheduler);
/* enable iommu */
rga_write(RGA_IOMMU_CMD_ENABLE_PAGING, RGA_IOMMU_COMMAND, scheduler);
}
@@ -2723,9 +2731,13 @@ static void rga2_soft_reset(struct rga_scheduler_t *scheduler)
if (i == RGA_RESET_TIMEOUT)
rga_err("%s[%#x] soft reset timeout.\n",
rga_get_core_name(scheduler->core), scheduler->core);
else
rga_log("%s[%#x] soft reset complete.\n",
rga_get_core_name(scheduler->core), scheduler->core);
}
static void rga2_soft_reset_print(struct rga_scheduler_t *scheduler)
{
rga2_soft_reset(scheduler);
rga_log("%s[%#x] soft reset complete.\n",
rga_get_core_name(scheduler->core), scheduler->core);
}
static int rga2_check_param(struct rga_job *job,
@@ -3023,6 +3035,27 @@ static void rga2_dump_read_back_cmd_reg(struct rga_job *job, struct rga_schedule
cmd_reg[2 + i * 4], cmd_reg[3 + i * 4]);
}
static void rga2_dump_read_back_iommu_reg(struct rga_job *job, struct rga_scheduler_t *scheduler)
{
int i;
unsigned long flags;
uint32_t cmd_reg[12] = {0};
spin_lock_irqsave(&scheduler->irq_lock, flags);
for (i = 0; i < 12; i++)
cmd_reg[i] = rga_read(RGA2_IOMMU_REG_BASE + i * 4, scheduler);
spin_unlock_irqrestore(&scheduler->irq_lock, flags);
rga_job_log(job, "IOMMU_READ_BACK_REG\n");
for (i = 0; i < 3; i++)
rga_job_log(job, "0x%04x : %.8x %.8x %.8x %.8x\n",
RGA2_IOMMU_REG_BASE + i * 0x10,
cmd_reg[0 + i * 4], cmd_reg[1 + i * 4],
cmd_reg[2 + i * 4], cmd_reg[3 + i * 4]);
}
static void rga2_dump_read_back_reg(struct rga_job *job, struct rga_scheduler_t *scheduler)
{
rga2_dump_read_back_sys_reg(job, scheduler);
@@ -3030,6 +3063,7 @@ static void rga2_dump_read_back_reg(struct rga_job *job, struct rga_scheduler_t
if (scheduler->data->version > 0)
rga2_dump_read_back_other_reg(job, scheduler);
rga2_dump_read_back_cmd_reg(job, scheduler);
rga2_dump_read_back_iommu_reg(job, scheduler);
}
static void rga2_set_pre_intr_reg(struct rga_job *job, struct rga_scheduler_t *scheduler)
@@ -3120,6 +3154,7 @@ static int rga2_set_reg(struct rga_job *job, struct rga_scheduler_t *scheduler)
RGA2_CMD_REG_BASE + i * 0x10,
cmd[0 + i * 4], cmd[1 + i * 4],
cmd[2 + i * 4], cmd[3 + i * 4]);
rga2_dump_read_back_iommu_reg(scheduler->running_job, scheduler);
}
spin_lock_irqsave(&scheduler->irq_lock, flags);
@@ -3132,12 +3167,11 @@ static int rga2_set_reg(struct rga_job *job, struct rga_scheduler_t *scheduler)
sys_ctrl |= m_RGA2_SYS_CTRL_DST_WR_OPT_DIS | m_RGA2_SRC0_YUV420SP_RD_OPT_DIS;
if (rga_hw_has_issue(scheduler, RGA_HW_ISSUE_DIS_AUTO_RST)) {
/*
* when RGA is running continuously, disabling auto_rst
* requires resetting core_clk.
*/
rga_write(m_RGA2_SYS_CTRL_AUTO_CKG | m_RGA2_SYS_CTRL_CCLK_SRESET_P,
RGA2_SYS_CTRL, scheduler);
/* disable all_finish & cur_finish intr_en */
rga_write(0, RGA2_INT, scheduler);
rga_write(0, RGA2_CMD_REG_BASE + RGA2_MODE_CTRL_OFFSET, scheduler);
/* replace auto_rst */
rga2_soft_reset(scheduler);
} else {
sys_ctrl |= m_RGA2_SYS_CTRL_AUTO_RST;
}
@@ -3346,7 +3380,7 @@ const struct rga_backend_ops rga2_ops = {
.get_version = rga2_get_version,
.set_reg = rga2_set_reg,
.init_reg = rga2_init_reg,
.soft_reset = rga2_soft_reset,
.soft_reset = rga2_soft_reset_print,
.read_back_reg = rga2_read_back_reg,
.read_status = rga2_read_status,
.irq = rga2_irq,

View File

@@ -2089,6 +2089,27 @@ static void rga3_dump_read_back_reg(struct rga_job *job, struct rga_scheduler_t
cmd_reg[2 + i * 4], cmd_reg[3 + i * 4]);
}
static void rga3_dump_read_back_iommu_reg(struct rga_job *job, struct rga_scheduler_t *scheduler)
{
int i;
unsigned long flags;
uint32_t cmd_reg[12] = {0};
spin_lock_irqsave(&scheduler->irq_lock, flags);
for (i = 0; i < 12; i++)
cmd_reg[i] = rga_read(RGA3_IOMMU_REG_BASE + i * 4, scheduler);
spin_unlock_irqrestore(&scheduler->irq_lock, flags);
rga_job_log(job, "IOMMU_READ_BACK_REG\n");
for (i = 0; i < 3; i++)
rga_job_log(job, "0x%04x : %.8x %.8x %.8x %.8x\n",
RGA3_IOMMU_REG_BASE + i * 0x10,
cmd_reg[0 + i * 4], cmd_reg[1 + i * 4],
cmd_reg[2 + i * 4], cmd_reg[3 + i * 4]);
}
static int rga3_set_reg(struct rga_job *job, struct rga_scheduler_t *scheduler)
{
int i;
@@ -2117,6 +2138,8 @@ static int rga3_set_reg(struct rga_job *job, struct rga_scheduler_t *scheduler)
RGA3_CMD_REG_BASE + i * 0x10,
cmd[0 + i * 4], cmd[1 + i * 4],
cmd[2 + i * 4], cmd[3 + i * 4]);
rga3_dump_read_back_iommu_reg(job, scheduler);
}
/* All CMD finish int */
@@ -2151,6 +2174,7 @@ static int rga3_set_reg(struct rga_job *job, struct rga_scheduler_t *scheduler)
if (DEBUGGER_EN(REG)) {
rga3_dump_read_back_sys_reg(job, scheduler);
rga3_dump_read_back_reg(job, scheduler);
rga3_dump_read_back_iommu_reg(job, scheduler);
}
return 0;