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Merge "ODROID-COMMON: hdmitx: Adjust 2560x1600 timing to use lower pixel clock" into odroidg12-4.9.y

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This commit is contained in:
Joy Cho
2020-09-24 10:35:13 +09:00
committed by Gerrit Code Review
parent 04f0d87806 5695340a34
commit cbb49c05e1
5 changed files with 100 additions and 9 deletions
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50
drivers/amlogic/media/vout/hdmitx/hdmi_common/hdmi_parameters.c
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@@ -2835,6 +2835,55 @@ static struct hdmi_format_para fmt_para_vesa_2160x1200p90_9x5 = {
},
};
#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
static struct hdmi_format_para fmt_para_vesa_2560x1600p60_8x5 = {
.vic = HDMIV_2560x1600p60hz,
.name = "2560x1600p60hz",
.pixel_repetition_factor = 0,
.progress_mode = 1,
.scrambler_en = 0,
.tmds_clk_div40 = 0,
.tmds_clk = 268000,
.timing = {
.pixel_freq = 268000,
.h_freq = 98529,
.v_freq = 59859,
.vsync = 60,
.vsync_polarity = 1,
.hsync_polarity = 0,
.h_active = 2560,
.h_total = 2720,
.h_blank = 160,
.h_front = 48,
.h_sync = 32,
.h_back = 80,
.v_active = 1600,
.v_total = 1646,
.v_blank = 46,
.v_front = 2,
.v_sync = 6,
.v_back = 38,
.v_sync_ln = 1,
},
.hdmitx_vinfo = {
.name = "2560x1600p60hz",
.mode = VMODE_HDMI,
.width = 2560,
.height = 1600,
.field_height = 1600,
.aspect_ratio_num = 8,
.aspect_ratio_den = 5,
.sync_duration_num = 60,
.sync_duration_den = 1,
.video_clk = 268000000,
.htotal = 2720,
.vtotal = 1646,
.fr_adj_type = VOUT_FR_ADJ_HDMI,
.viu_color_fmt = COLOR_FMT_YUV444,
.viu_mux = VIU_MUX_ENCP,
},
};
#else
static struct hdmi_format_para fmt_para_vesa_2560x1600p60_8x5 = {
.vic = HDMIV_2560x1600p60hz,
.name = "2560x1600p60hz",
@@ -2882,6 +2931,7 @@ static struct hdmi_format_para fmt_para_vesa_2560x1600p60_8x5 = {
.viu_mux = VIU_MUX_ENCP,
},
};
#endif /* CONFIG_ARCH_MESON64_ODROID_COMMON */
static struct hdmi_format_para *all_fmt_paras[] = {
&fmt_para_3840x2160p60_16x9,

28
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/enc_cfg_hw.c
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@@ -1284,6 +1284,33 @@ static const struct reg_s tvregs_vesa_2160x1200p90hz[] = {
{MREG_END_MARKER, 0},
};
#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
static const struct reg_s tvregs_vesa_2560x1600p60hz[] = {
{P_VENC_VDAC_SETTING, 0xff,},
{P_ENCP_VIDEO_EN, 0,},
{P_ENCI_VIDEO_EN, 0,},
{P_ENCP_VIDEO_MODE, 0x4040,},
{P_ENCP_VIDEO_MODE_ADV, 0x18,},
{P_ENCP_VIDEO_MAX_PXCNT, 0xA9F,},
{P_ENCP_VIDEO_MAX_LNCNT, 0x66D,},
{P_ENCP_VIDEO_HAVON_BEGIN, 0x50,},
{P_ENCP_VIDEO_HAVON_END, 0xA4F,},
{P_ENCP_VIDEO_VAVON_BLINE, 0x26,},
{P_ENCP_VIDEO_VAVON_ELINE, 0x665,},
{P_ENCP_VIDEO_HSO_BEGIN, 0,},
{P_ENCP_VIDEO_HSO_END, 0x20,},
{P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
{P_ENCP_VIDEO_VSO_END, 0x32,},
{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
{P_ENCP_VIDEO_VSO_ELINE, 0x6,},
{P_ENCP_VIDEO_EN, 1,},
{P_ENCI_VIDEO_EN, 0,},
{MREG_END_MARKER, 0},
};
#else
static const struct reg_s tvregs_vesa_2560x1600p60hz[] = {
{P_ENCP_VIDEO_EN, 0,},
{P_ENCI_VIDEO_EN, 0,},
@@ -1308,6 +1335,7 @@ static const struct reg_s tvregs_vesa_2560x1600p60hz[] = {
{P_ENCI_VIDEO_EN, 0},
{MREG_END_MARKER, 0}
};
#endif
#if 0 /* TODO */
static const struct reg_s tvregs_vesa_2560x1080p60hz[] = {

16
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c
View File

@@ -1744,14 +1744,14 @@ static void hdmi_tvenc_set(struct hdmitx_vidpara *param)
PIXEL_REPEAT_HDMI = 0;
ACTIVE_PIXELS = (2560*(1+PIXEL_REPEAT_HDMI));
ACTIVE_LINES = (1600/(1+INTERLACE_MODE));
LINES_F0 = 1658;
LINES_F1 = 1658;
FRONT_PORCH = 192;
HSYNC_PIXELS = 280;
BACK_PORCH = 472;
EOF_LINES = 3;
VSYNC_LINES = 6;
SOF_LINES = 49;
LINES_F0 = 1646;
LINES_F1 = 1646;
FRONT_PORCH = 48;
HSYNC_PIXELS = 32;
BACK_PORCH = 80;
EOF_LINES = 2;
VSYNC_LINES = 3;
SOF_LINES = 19;
TOTAL_FRAMES = 4;
break;
case HDMIV_2560x1440p60hz:

2
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c
View File

@@ -943,7 +943,7 @@ static struct hw_enc_clk_val_group setting_enc_clk_val_24[] = {
{{HDMIV_2560x1600p60hz,
HDMI_VIC_END},
#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
3450000, 1, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
5370000, 2, 1, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
#else
3485000, 1, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
#endif

13
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c
View File

@@ -349,6 +349,19 @@ void set_g12a_hpll_clk_out(unsigned int frac_rate, unsigned int clk)
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
break;
#if defined(CONFIG_ARCH_MESON64_ODROID_COMMON)
case 5370000:
/* stability issue : 5370000 (0xdf) -> 5360000 (0xde) */
hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004de);
hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00000000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
break;
case 3197500:
hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b000485);
if (frac_rate)