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drm/bridge: analogix_dp: Add NULL pointer check for dp->phy

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Fixes: d7ad116fb3 ("drm/rockchip: analogix_dp: Add support for rk3568")
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I8cef87e13dd7c03baac730523c8f4b98d1a043f2
This commit is contained in:
Wyon Bi
2020-11-18 19:09:58 +08:00
committed by Tao Huang
parent 66d48911ac
commit cbee98b758
1 changed files with 54 additions and 45 deletions
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99
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
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@@ -626,7 +626,6 @@ bool analogix_dp_ssc_supported(struct analogix_dp_device *dp)
void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype)
{
union phy_configure_opts phy_cfg;
u32 reg, status;
int ret;
@@ -634,18 +633,21 @@ void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype)
if ((bwtype == DP_LINK_BW_2_7) || (bwtype == DP_LINK_BW_1_62))
analogix_dp_write(dp, ANALOGIX_DP_LINK_BW_SET, reg);
phy_cfg.dp.lanes = dp->link_train.lane_count;
phy_cfg.dp.link_rate =
drm_dp_bw_code_to_link_rate(dp->link_train.link_rate) / 100;
phy_cfg.dp.ssc = analogix_dp_ssc_supported(dp);
phy_cfg.dp.set_lanes = false;
phy_cfg.dp.set_rate = true;
phy_cfg.dp.set_voltages = false;
ret = phy_configure(dp->phy, &phy_cfg);
if (ret && ret != -EOPNOTSUPP) {
dev_err(dp->dev, "%s: phy_configure() failed: %d\n",
__func__, ret);
return;
if (dp->phy) {
union phy_configure_opts phy_cfg;
phy_cfg.dp.lanes = dp->link_train.lane_count;
phy_cfg.dp.link_rate = drm_dp_bw_code_to_link_rate(dp->link_train.link_rate) / 100;
phy_cfg.dp.ssc = analogix_dp_ssc_supported(dp);
phy_cfg.dp.set_lanes = false;
phy_cfg.dp.set_rate = true;
phy_cfg.dp.set_voltages = false;
ret = phy_configure(dp->phy, &phy_cfg);
if (ret && ret != -EOPNOTSUPP) {
dev_err(dp->dev, "%s: phy_configure() failed: %d\n",
__func__, ret);
return;
}
}
ret = readx_poll_timeout(analogix_dp_get_pll_lock_status, dp, status,
@@ -667,22 +669,25 @@ void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype)
void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count)
{
union phy_configure_opts phy_cfg;
u32 reg;
int ret;
reg = count;
analogix_dp_write(dp, ANALOGIX_DP_LANE_COUNT_SET, reg);
phy_cfg.dp.lanes = dp->link_train.lane_count;
phy_cfg.dp.set_lanes = true;
phy_cfg.dp.set_rate = false;
phy_cfg.dp.set_voltages = false;
ret = phy_configure(dp->phy, &phy_cfg);
if (ret && ret != -EOPNOTSUPP) {
dev_err(dp->dev, "%s: phy_configure() failed: %d\n",
__func__, ret);
return;
if (dp->phy) {
union phy_configure_opts phy_cfg;
phy_cfg.dp.lanes = dp->link_train.lane_count;
phy_cfg.dp.set_lanes = true;
phy_cfg.dp.set_rate = false;
phy_cfg.dp.set_voltages = false;
ret = phy_configure(dp->phy, &phy_cfg);
if (ret && ret != -EOPNOTSUPP) {
dev_err(dp->dev, "%s: phy_configure() failed: %d\n",
__func__, ret);
return;
}
}
}
@@ -696,35 +701,39 @@ void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count)
void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp)
{
union phy_configure_opts phy_cfg;
u8 lane;
int ret;
for (lane = 0; lane < dp->link_train.lane_count; lane++) {
u8 training_lane = dp->link_train.training_lane[lane];
u8 vs, pe;
for (lane = 0; lane < dp->link_train.lane_count; lane++)
analogix_dp_write(dp,
ANALOGIX_DP_LN0_LINK_TRAINING_CTL + 4 * lane,
training_lane);
dp->link_train.training_lane[lane]);
vs = (training_lane >> DP_TRAIN_VOLTAGE_SWING_SHIFT) &
DP_TRAIN_VOLTAGE_SWING_MASK;
pe = (training_lane >> DP_TRAIN_PRE_EMPHASIS_SHIFT) &
DP_TRAIN_PRE_EMPHASIS_MASK;
phy_cfg.dp.voltage[lane] = vs;
phy_cfg.dp.pre[lane] = pe;
}
if (dp->phy) {
union phy_configure_opts phy_cfg;
phy_cfg.dp.lanes = dp->link_train.lane_count;
phy_cfg.dp.set_lanes = false;
phy_cfg.dp.set_rate = false;
phy_cfg.dp.set_voltages = true;
ret = phy_configure(dp->phy, &phy_cfg);
if (ret && ret != -EOPNOTSUPP) {
dev_err(dp->dev, "%s: phy_configure() failed: %d\n",
__func__, ret);
return;
for (lane = 0; lane < dp->link_train.lane_count; lane++) {
u8 training_lane = dp->link_train.training_lane[lane];
u8 vs, pe;
vs = (training_lane >> DP_TRAIN_VOLTAGE_SWING_SHIFT) &
DP_TRAIN_VOLTAGE_SWING_MASK;
pe = (training_lane >> DP_TRAIN_PRE_EMPHASIS_SHIFT) &
DP_TRAIN_PRE_EMPHASIS_MASK;
phy_cfg.dp.voltage[lane] = vs;
phy_cfg.dp.pre[lane] = pe;
}
phy_cfg.dp.lanes = dp->link_train.lane_count;
phy_cfg.dp.set_lanes = false;
phy_cfg.dp.set_rate = false;
phy_cfg.dp.set_voltages = true;
ret = phy_configure(dp->phy, &phy_cfg);
if (ret && ret != -EOPNOTSUPP) {
dev_err(dp->dev, "%s: phy_configure() failed: %d\n",
__func__, ret);
return;
}
}
}