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pinctrl: rockchip: fix rk3288 gpio0 configuration

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On rk3288, for gpio bank 0, the registers which configure pull-up,
iomux, and drive strength don't implement the enable bits in the upper
half of the register, unlike the other gpio configuration registers,
and so the kernel must perform a read-modify-write of the register to
update a particular gpio in that bank.

Change-Id: I4a6953839307e3a75b2ac554aac3dc865583617d
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
This commit is contained in:
Chris Zhong
2015-09-02 15:59:38 +08:00
committed by Huang, Tao
parent 92e7da2818
commit cbf1d23ba5
1 changed files with 18 additions and 7 deletions
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25
drivers/pinctrl/pinctrl-rockchip.c
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@@ -1366,8 +1366,14 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
case RK3288:
spin_lock_irqsave(&bank->slock, flags);
/* enable the write to the equivalent lower bits */
data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
/* enable the write to the equivalent lower bits,
* but gpio0 has not the write_enable bit.
*/
if (bank->bank_num == 0) {
data = readl_relaxed(reg);
data &= ~(3 << bit);
} else
data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
switch (pull) {
case PIN_CONFIG_BIAS_DISABLE:
@@ -1746,10 +1752,15 @@ static int _rockchip_pinconf_set(struct rockchip_pin_bank *bank,
spin_lock_irqsave(&bank->slock, flags);
data = arg << bit;
data &= (3<<bit);
data |= (3<<(bit+16));
if (bank->bank_num == 0) {
data = readl_relaxed(reg);
data &= ~(3<<bit);
data |= arg << bit;
} else {
data = arg << bit;
data |= (3<<(bit+16));
}
writel_relaxed(data, reg);
spin_unlock_irqrestore(&bank->slock, flags);
@@ -3368,7 +3379,7 @@ static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
static struct rockchip_pin_bank rk3288_pin_banks[] = {
PIN_BANK(0, 32, "gpio0"),
PIN_BANK(0, 24, "gpio0"),
PIN_BANK(1, 32, "gpio1"),
PIN_BANK(2, 32, "gpio2"),
PIN_BANK(3, 32, "gpio3"),