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phy: rockchip-snps-pcie3: update fw when init

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This fw fix some RX issue:
1. connect detect error;
2. transfer error in ssd huge data write(more than 10GB).

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: If9b8d7fbe4414ae4d28ff6bbd4415d88b582113d
This commit is contained in:
Kever Yang
2022-05-13 09:54:12 +08:00
committed by Tao Huang
parent 1b493c5412
commit cbf3eb9b7f
2 changed files with 8218 additions and 2 deletions
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28
drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
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@@ -21,6 +21,7 @@
/* Register for RK3568 */
#define GRF_PCIE30PHY_CON1 0x4
#define GRF_PCIE30PHY_CON4 0x10
#define GRF_PCIE30PHY_CON6 0x18
#define GRF_PCIE30PHY_CON9 0x24
#define GRF_PCIE30PHY_STATUS0 0x80
@@ -78,8 +79,13 @@ static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int subm
return 0;
}
static const u16 phy_fw[] = {
#include "phy-rockchip-snps-pcie3.fw"
};
static int rockchip_p3phy_rk3568_init(struct rockchip_p3phy_priv *priv)
{
int i;
int ret = 0;
u32 reg;
@@ -93,16 +99,34 @@ static int rockchip_p3phy_rk3568_init(struct rockchip_p3phy_priv *priv)
regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON1,
(0x1 << 15) | (0x1 << 31));
}
regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4,
(0x0 << 14) | (0x1 << (14 + 16))); //sdram_ld_done
regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4,
(0x0 << 13) | (0x1 << (13 + 16))); //sdram_bypass
reset_control_deassert(priv->p30phy);
ret = regmap_read_poll_timeout(priv->phy_grf,
GRF_PCIE30PHY_STATUS0,
reg, SRAM_INIT_DONE(reg),
0, 500);
if (ret)
if (ret) {
pr_err("%s: lock failed 0x%x, check input refclk and power supply\n",
__func__, reg);
goto out;
}
regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9,
(0x3 << 8) | (0x3 << (8 + 16))); //map to access sram
for (i = 0; i < ARRAY_SIZE(phy_fw); i++)
writel(phy_fw[i], priv->mmio + (i<<2));
pr_info("snps pcie3phy FW update! size %ld\n", ARRAY_SIZE(phy_fw));
regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9,
(0x0 << 8) | (0x3 << (8 + 16)));
regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4,
(0x1 << 14) | (0x1 << (14 + 16))); //sdram_ld_done
out:
return ret;
}

8192
drivers/phy/rockchip/phy-rockchip-snps-pcie3.fw Normal file
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