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media: rockchip: isp: fix isp39

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1.fix lsc error of first frame
2.fix scl update hold when isp working
3.fix resolution config for unite mode
4.resume to restore dhaz iir data

Change-Id: I070b0dbef0eef404d040dedf4555cc7fe335de6f
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
This commit is contained in:
Cai YiWei
2024-03-07 17:55:02 +08:00
committed by cain.cai
parent 01c843bf96
commit cc191263a7
15 changed files with 146 additions and 70 deletions
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16
drivers/media/platform/rockchip/isp/capture.c
View File

@@ -450,6 +450,22 @@ int rkisp_stream_frame_start(struct rkisp_device *dev, u32 isp_mis)
return 0;
}
int rkisp_stream_isp_end(struct rkisp_device *dev, u32 isp_mis)
{
struct rkisp_stream *stream;
int i;
for (i = 0; i < RKISP_MAX_STREAM; i++) {
if (i == RKISP_STREAM_VIR || i == RKISP_STREAM_LUMA)
continue;
stream = &dev->cap_dev.stream[i];
if (stream->streaming &&
stream->ops && stream->ops->isp_end)
stream->ops->isp_end(stream, isp_mis);
}
return 0;
}
void rkisp_stream_buf_done_early(struct rkisp_device *dev)
{
struct rkisp_stream *stream;

3
drivers/media/platform/rockchip/isp/capture.h
View File

@@ -242,6 +242,7 @@ struct streams_ops {
int (*frame_end)(struct rkisp_stream *stream, u32 state);
int (*frame_start)(struct rkisp_stream *stream, u32 mis);
int (*set_wrap)(struct rkisp_stream *stream, int line);
int (*isp_end)(struct rkisp_stream *stream, u32 irq);
};
struct rockit_isp_ops {
@@ -301,6 +302,7 @@ struct rkisp_stream {
bool is_crop_upd;
bool is_using_resmem;
bool frame_early;
bool need_scl_upd;
wait_queue_head_t done;
unsigned int burst;
atomic_t sequence;
@@ -354,6 +356,7 @@ void rkisp_mi_isr(u32 mis_val, struct rkisp_device *dev);
void rkisp_set_stream_def_fmt(struct rkisp_device *dev, u32 id,
u32 width, u32 height, u32 pixelformat);
int rkisp_stream_frame_start(struct rkisp_device *dev, u32 isp_mis);
int rkisp_stream_isp_end(struct rkisp_device *dev, u32 isp_mis);
int rkisp_fcc_xysubs(u32 fcc, u32 *xsubs, u32 *ysubs);
int rkisp_mbus_code_xysubs(u32 code, u32 *xsubs, u32 *ysubs);
int rkisp_fh_open(struct file *filp);

33
drivers/media/platform/rockchip/isp/capture_v39.c
View File

@@ -23,6 +23,7 @@
static int mi_frame_end(struct rkisp_stream *stream, u32 state);
static int mi_frame_start(struct rkisp_stream *stream, u32 irq);
static int isp_frame_end(struct rkisp_stream *stream, u32 irq);
static const struct capture_fmt mp_fmts[] = {
/* yuv422 */
@@ -847,7 +848,7 @@ static void update_mi(struct rkisp_stream *stream)
rkisp_write(dev, reg, val, false);
}
if (dev->hw_dev->unite > ISP_UNITE_DIV1) {
if (dev->unite_div > ISP_UNITE_DIV1) {
/* right of image, or right top of image */
reg = stream->config->mi.y_base_ad_init;
val = stream->next_buf->buff_addr[RKISP_PLANE_Y];
@@ -934,6 +935,7 @@ static struct streams_ops rkisp_mp_streams_ops = {
.update_mi = update_mi,
.frame_end = mi_frame_end,
.frame_start = mi_frame_start,
.isp_end = isp_frame_end,
};
static struct streams_ops rkisp_sp_streams_ops = {
@@ -945,6 +947,7 @@ static struct streams_ops rkisp_sp_streams_ops = {
.update_mi = update_mi,
.frame_end = mi_frame_end,
.frame_start = mi_frame_start,
.isp_end = isp_frame_end,
};
static struct streams_ops rkisp_ldc_streams_ops = {
@@ -1007,6 +1010,24 @@ static int mi_frame_start(struct rkisp_stream *stream, u32 irq)
return 0;
}
static int isp_frame_end(struct rkisp_stream *stream, u32 irq)
{
struct rkisp_device *dev = stream->ispdev;
u32 val = ISP3X_ISP_OUT_LINE(rkisp_read(dev, ISP3X_ISP_DEBUG2, true));
if (stream->need_scl_upd) {
if (val)
v4l2_err(&dev->v4l2_dev,
"no to update scl, need to increase sensor vblank\n");
else {
val = ISP32_SCALE_FORCE_UPD | ISP32_SCALE_GEN_UPD;
rkisp_write(dev, stream->config->rsz.update, val, true);
stream->need_scl_upd = false;
}
}
return 0;
}
/*
* This function is called when a frame end come. The next frame
* is processing and we should set up buffer for next-next frame,
@@ -1461,11 +1482,16 @@ static int rkisp_stream_start(struct rkisp_stream *stream)
{
struct rkisp_device *dev = stream->ispdev;
struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
bool async = false;
int ret;
stream->need_scl_upd = false;
if (stream->id == RKISP_STREAM_LDC)
goto skip;
async = (dev->cap_dev.stream[RKISP_STREAM_MP].streaming ||
dev->cap_dev.stream[RKISP_STREAM_SP].streaming);
/*
* can't be async now, otherwise the latter started stream fails to
* produce mi interrupt.
@@ -1476,12 +1502,13 @@ static int rkisp_stream_start(struct rkisp_stream *stream)
return ret;
}
ret = rkisp_stream_config_rsz(stream, false);
ret = rkisp_stream_config_rsz(stream, async);
if (ret < 0) {
v4l2_err(v4l2_dev, "config rsz failed with error %d\n", ret);
return ret;
}
if (async && dev->hw_dev->is_single)
stream->need_scl_upd = true;
skip:
return rkisp_start(stream);
}

5
drivers/media/platform/rockchip/isp/dev.c
View File

@@ -1171,9 +1171,10 @@ static void rkisp_pm_complete(struct device *dev)
isp_dev->isp_state = ISP_START | ISP_FRAME_END;
if (!hw->is_single && hw->is_multi_overflow)
hw->pre_dev_id++;
if (isp_dev->is_suspend_one_frame && !hw->is_multi_overflow)
if (isp_dev->is_suspend_one_frame &&
!hw->is_multi_overflow && hw->isp_ver < ISP_V33)
isp_dev->is_first_double = true;
if (hw->isp_ver > ISP_V20) {
if (hw->isp_ver > ISP_V20 && hw->isp_ver < ISP_V33) {
val = ISP3X_YNR_FST_FRAME | ISP3X_CNR_FST_FRAME |
ISP3X_DHAZ_FST_FRAME | ISP3X_ADRC_FST_FRAME;
if (hw->isp_ver == ISP_V32)

70
drivers/media/platform/rockchip/isp/hw.c
View File

@@ -417,6 +417,21 @@ void rkisp_hw_reg_restore(struct rkisp_hw_dev *dev)
}, {
.base = MI_WR_CTRL,
.shd = MI_WR_CTRL_SHD,
}, {
.base = ISP39_W3A_AEBIG_ADDR,
.shd = ISP39_W3A_AEBIG_ADDR_SHD,
}, {
.base = ISP39_W3A_AE0_ADDR,
.shd = ISP39_W3A_AE0_ADDR_SHD,
}, {
.base = ISP39_W3A_AF_ADDR,
.shd = ISP39_W3A_AF_ADDR_SHD,
}, {
.base = ISP39_W3A_AWB_ADDR,
.shd = ISP39_W3A_AWB_ADDR_SHD,
}, {
.base = ISP39_W3A_PDAF_ADDR,
.shd = ISP39_W3A_PDAF_ADDR_SHD,
}
};
@@ -438,6 +453,11 @@ void rkisp_hw_reg_restore(struct rkisp_hw_dev *dev)
*reg = 1;
}
}
if (dev->isp_ver == ISP_V39) {
reg = reg_buf + ISP39_VI3A_CTRL0;
if (*reg)
*reg |= ISP39_W3A_FORCE_UPD;
}
reg = reg_buf + ISP_CTRL;
*reg &= ~(CIF_ISP_CTRL_ISP_ENABLE |
CIF_ISP_CTRL_ISP_INFORM_ENABLE |
@@ -451,7 +471,9 @@ void rkisp_hw_reg_restore(struct rkisp_hw_dev *dev)
if ((j > ISP3X_LSC_CTRL && j < ISP3X_LSC_XGRAD_01) ||
(j > ISP32_CAC_OFFSET && j < ISP3X_CAC_RO_CNT) ||
(j > ISP3X_3DLUT_UPDATE && j < ISP3X_GAIN_BASE) ||
(j == 0x4840 || j == 0x4a80 || j == 0x4b40 || j == 0x5660))
(j == 0x4840 || j == 0x4a80 || j == 0x4b40 || j == 0x5660) ||
(dev->isp_ver == ISP_V39 &&
(j > ISP39_DHAZ_HIST_IIR0 && j < ISP39_DHAZ_LINE_CNT)))
continue;
/* skip mmu range */
if (dev->isp_ver < ISP_V30 &&
@@ -479,7 +501,7 @@ void rkisp_hw_reg_restore(struct rkisp_hw_dev *dev)
}
writel(val, base + backup[j].base);
}
if (dev->isp_ver == ISP_V30) {
if (dev->isp_ver == ISP_V32) {
reg = reg_buf + ISP32_MI_WR_CTRL2_SHD;
reg1 = reg_buf + ISP3X_MI_BP_WR_CTRL;
if ((*reg & ISP32_BP_EN_IN_SHD) != (*reg1 & ISP3X_BP_ENABLE)) {
@@ -507,25 +529,38 @@ void rkisp_hw_reg_restore(struct rkisp_hw_dev *dev)
writel(*reg | CIF_DUAL_CROP_CFG_UPD, base + DUAL_CROP_CTRL);
reg = reg_buf + SELF_RESIZE_CTRL;
if (*reg & 0xf) {
if (dev->isp_ver == ISP_V32_L)
writel(*reg | ISP32_SCALE_FORCE_UPD, base + ISP32_SELF_SCALE_UPDATE);
if (dev->isp_ver == ISP_V32_L || dev->isp_ver == ISP_V39)
writel(ISP32_SCALE_FORCE_UPD | ISP32_SCALE_GEN_UPD,
base + ISP32_SELF_SCALE_UPDATE);
else
writel(*reg | CIF_RSZ_CTRL_CFG_UPD, base + SELF_RESIZE_CTRL);
}
reg = reg_buf + MAIN_RESIZE_CTRL;
if (*reg & 0xf)
writel(*reg | CIF_RSZ_CTRL_CFG_UPD, base + MAIN_RESIZE_CTRL);
if (*reg & 0xf) {
if (dev->isp_ver == ISP_V39)
writel(ISP32_SCALE_FORCE_UPD | ISP32_SCALE_GEN_UPD,
base + ISP39_MAIN_SCALE_UPDATE);
else
writel(*reg | CIF_RSZ_CTRL_CFG_UPD, base + MAIN_RESIZE_CTRL);
}
reg = reg_buf + ISP32_BP_RESIZE_CTRL;
if (*reg & 0xf)
writel(*reg | CIF_RSZ_CTRL_CFG_UPD, base + ISP32_BP_RESIZE_CTRL);
if (dev->isp_ver == ISP_V39) {
reg = reg_buf + ISP39_W3A_CTRL0;
if (*reg)
writel(*reg | ISP39_W3A_FORCE_UPD, base + ISP39_W3A_CTRL0);
reg = reg_buf + ISP39_VI3A_CTRL0;
if (*reg)
writel(*reg | ISP39_W3A_FORCE_UPD, base + ISP39_VI3A_CTRL0);
}
/* update mi and isp, base_reg will update to shd_reg */
writel(CIF_MI_INIT_SOFT_UPD, base + MI_WR_INIT);
/* config base_reg */
for (j = 0; j < ARRAY_SIZE(backup); j++)
writel(backup[j].val, base + backup[j].base);
if (dev->isp_ver == ISP_V30) {
if (dev->isp_ver == ISP_V32) {
reg = reg_buf + ISP3X_MI_BP_WR_CTRL;
writel(*reg, base + ISP3X_MI_BP_WR_CTRL);
reg = reg_buf + ISP32_MI_MPDS_WR_CTRL;
@@ -540,15 +575,17 @@ void rkisp_hw_reg_restore(struct rkisp_hw_dev *dev)
writel(val, base + MI_SWS_3A_WR_BASE);
}
rkisp_params_cfgsram(&isp->params_vdev, false);
if (dev->is_single) {
rkisp_params_cfgsram(&isp->params_vdev, false, true);
reg = reg_buf + ISP_CTRL;
*reg |= CIF_ISP_CTRL_ISP_ENABLE |
CIF_ISP_CTRL_ISP_CFG_UPD |
CIF_ISP_CTRL_ISP_INFORM_ENABLE;
writel(*reg, dev->base_addr + ISP_CTRL);
if (dev->unite == ISP_UNITE_TWO)
writel(*reg, dev->base_next_addr + ISP_CTRL);
reg = reg_buf + ISP_CTRL;
*reg |= CIF_ISP_CTRL_ISP_ENABLE |
CIF_ISP_CTRL_ISP_CFG_UPD |
CIF_ISP_CTRL_ISP_INFORM_ENABLE;
writel(*reg, dev->base_addr + ISP_CTRL);
if (dev->unite == ISP_UNITE_TWO)
writel(*reg, dev->base_next_addr + ISP_CTRL);
}
}
static const char * const rk3562_isp_clks[] = {
@@ -964,6 +1001,7 @@ void rkisp_soft_reset(struct rkisp_hw_dev *dev, bool is_secure)
writel(ISP39_ADRC_CMPS_BYP_EN, dev->base_addr + ISP3X_DRC_CTRL0);
writel(ISP39_W3A_PDAF2DDR_HOLD_DIS | ISP39_W3A_3A_HOLD_DIS,
dev->base_addr + ISP39_W3A_CTRL0);
writel(0, dev->base_addr + ISP39_VI3A_CTRL0);
}
}

5
drivers/media/platform/rockchip/isp/isp_params.c
View File

@@ -404,7 +404,8 @@ void rkisp_params_cfg(struct rkisp_isp_params_vdev *params_vdev, u32 frame_id)
params_vdev->ops->param_cfg(params_vdev, frame_id, RKISP_PARAMS_IMD);
}
void rkisp_params_cfgsram(struct rkisp_isp_params_vdev *params_vdev, bool is_check)
void rkisp_params_cfgsram(struct rkisp_isp_params_vdev *params_vdev,
bool is_check, bool is_reset)
{
if (is_check) {
if (params_vdev->dev->procfs.mode & RKISP_PROCFS_FIL_SW)
@@ -415,7 +416,7 @@ void rkisp_params_cfgsram(struct rkisp_isp_params_vdev *params_vdev, bool is_che
return;
}
if (params_vdev->ops->param_cfgsram)
params_vdev->ops->param_cfgsram(params_vdev);
params_vdev->ops->param_cfgsram(params_vdev, is_reset);
}
void rkisp_params_isr(struct rkisp_isp_params_vdev *params_vdev,

4
drivers/media/platform/rockchip/isp/isp_params.h
View File

@@ -35,7 +35,7 @@ struct rkisp_isp_params_ops {
void (*isr_hdl)(struct rkisp_isp_params_vdev *params_vdev, u32 isp_mis);
void (*param_cfg)(struct rkisp_isp_params_vdev *params_vdev, u32 frame_id,
enum rkisp_params_type type);
void (*param_cfgsram)(struct rkisp_isp_params_vdev *params_vdev);
void (*param_cfgsram)(struct rkisp_isp_params_vdev *params_vdev, bool is_reset);
void (*get_meshbuf_inf)(struct rkisp_isp_params_vdev *params_vdev, void *meshbuf);
int (*set_meshbuf_size)(struct rkisp_isp_params_vdev *params_vdev, void *meshsize);
void (*free_meshbuf)(struct rkisp_isp_params_vdev *params_vdev, u64 id);
@@ -144,7 +144,7 @@ void rkisp_params_isr(struct rkisp_isp_params_vdev *params_vdev, u32 isp_mis);
void rkisp_params_cfg(struct rkisp_isp_params_vdev *params_vdev, u32 frame_id);
void rkisp_params_cfgsram(struct rkisp_isp_params_vdev *params_vdev, bool is_check);
void rkisp_params_cfgsram(struct rkisp_isp_params_vdev *params_vdev, bool is_check, bool is_reset);
void rkisp_params_get_meshbuf_inf(struct rkisp_isp_params_vdev *params_vdev, void *meshbuf);
int rkisp_params_set_meshbuf_size(struct rkisp_isp_params_vdev *params_vdev, void *meshsize);
void rkisp_params_meshbuf_free(struct rkisp_isp_params_vdev *params_vdev, u64 id);

2
drivers/media/platform/rockchip/isp/isp_params_v21.c
View File

@@ -3757,7 +3757,7 @@ void __isp_isr_meas_en(struct rkisp_isp_params_vdev *params_vdev,
}
static
void rkisp_params_cfgsram_v21(struct rkisp_isp_params_vdev *params_vdev)
void rkisp_params_cfgsram_v21(struct rkisp_isp_params_vdev *params_vdev, bool is_reset)
{
struct isp21_isp_params_cfg *params = params_vdev->isp21_params;

2
drivers/media/platform/rockchip/isp/isp_params_v2x.c
View File

@@ -4061,7 +4061,7 @@ void __isp_config_hdrshd(struct rkisp_isp_params_vdev *params_vdev)
}
static
void rkisp_params_cfgsram_v2x(struct rkisp_isp_params_vdev *params_vdev)
void rkisp_params_cfgsram_v2x(struct rkisp_isp_params_vdev *params_vdev, bool is_reset)
{
struct isp2x_isp_params_cfg *params = params_vdev->isp2x_params;

2
drivers/media/platform/rockchip/isp/isp_params_v32.c
View File

@@ -4379,7 +4379,7 @@ void __isp_isr_meas_en(struct rkisp_isp_params_vdev *params_vdev,
}
static
void rkisp_params_cfgsram_v32(struct rkisp_isp_params_vdev *params_vdev)
void rkisp_params_cfgsram_v32(struct rkisp_isp_params_vdev *params_vdev, bool is_reset)
{
u32 id = params_vdev->dev->unite_index;
struct isp32_isp_params_cfg *params = params_vdev->isp32_params + id;

21
drivers/media/platform/rockchip/isp/isp_params_v39.c
View File

@@ -633,6 +633,8 @@ isp_lsc_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
if (en) {
val = ISP_LSC_EN | ISP39_SELF_FORCE_UPD;
if (!IS_HDR_RDBK(params_vdev->dev->rd_mode))
val |= ISP3X_LSC_LUT_EN;
isp3_param_set_bits(params_vdev, ISP3X_LSC_CTRL, val, id);
} else {
isp3_param_clear_bits(params_vdev, ISP3X_LSC_CTRL, ISP_LSC_EN, id);
@@ -2342,7 +2344,7 @@ isp_dhaz_cfg_sram(struct rkisp_isp_params_vdev *params_vdev,
struct rkisp_isp_params_val_v39 *priv_val = params_vdev->priv_val;
u32 i, j, val, ctrl = isp3_param_read(params_vdev, ISP3X_DHAZ_CTRL, id);
if (is_check && (ctrl & ISP3X_DHAZ_ENMUX))
if (is_check && !(ctrl & ISP3X_DHAZ_ENMUX))
return;
if (arg->hist_iir_wr) {
@@ -2368,7 +2370,7 @@ isp_dhaz_config(struct rkisp_isp_params_vdev *params_vdev,
struct isp39_isp_params_cfg *params_rec = params_vdev->isp39_params + id;
struct isp39_dhaz_cfg *arg_rec = &params_rec->others.dhaz_cfg;
struct rkisp_isp_params_val_v39 *priv_val = params_vdev->priv_val;
u32 w = out_crop->width, h = out_crop->height;
u32 w = out_crop->width, h = out_crop->height;
u32 i, value, ctrl, thumb_row, thumb_col, blk_het, blk_wid;
ctrl = isp3_param_read(params_vdev, ISP3X_DHAZ_CTRL, id);
@@ -3361,7 +3363,9 @@ isp_bay3d_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
isp3_param_write(params_vdev, bay3d_ctrl, ISP3X_BAY3D_CTRL, id);
value = ISP3X_BAY3D_IIR_WR_AUTO_UPD | ISP3X_BAY3D_IIRSELF_UPD |
ISP3X_BAY3D_RDSELF_UPD | ISP3X_GAIN_WR_AUTO_UPD | ISP3X_GAINSELF_UPD;
ISP3X_BAY3D_RDSELF_UPD;
if (priv_val->buf_gain.mem_priv)
value |= ISP3X_GAIN_WR_AUTO_UPD | ISP3X_GAINSELF_UPD;
isp3_param_set_bits(params_vdev, MI_WR_CTRL2, value, id);
isp3_param_set_bits(params_vdev, ISP3X_ISP_CTRL1, ISP3X_RAW3D_FST_FRAME, id);
@@ -4090,12 +4094,17 @@ void __isp_isr_meas_en(struct rkisp_isp_params_vdev *params_vdev,
}
static
void rkisp_params_cfgsram_v39(struct rkisp_isp_params_vdev *params_vdev)
void rkisp_params_cfgsram_v39(struct rkisp_isp_params_vdev *params_vdev, bool is_reset)
{
u32 id = params_vdev->dev->unite_index;
struct rkisp_device *dev = params_vdev->dev;
u32 id = dev->unite_index;
struct isp39_isp_params_cfg *params = params_vdev->isp39_params + id;
if (!dev->hw_dev->is_frm_buf && is_reset)
params->others.dhaz_cfg.hist_iir_wr = true;
isp_dhaz_cfg_sram(params_vdev, &params->others.dhaz_cfg, true, id);
params->others.dhaz_cfg.hist_iir_wr = false;
isp_lsc_matrix_cfg_sram(params_vdev, &params->others.lsc_cfg, true, id);
isp_rawhstbig_cfg_sram(params_vdev, &params->meas.rawhist0,
ISP3X_RAWHIST_LITE_BASE, true, id);
@@ -4171,7 +4180,7 @@ rkisp_alloc_internal_buf(struct rkisp_isp_params_vdev *params_vdev,
priv_val->gain_size = val;
if (dev->unite_div > ISP_UNITE_DIV1)
val *= dev->unite_div;
is_alloc = iirsparse_en ? true : false;
is_alloc = dev->is_aiisp_en ? true : false;
if (priv_val->buf_gain.mem_priv) {
if (val > priv_val->buf_gain.size)
rkisp_free_buffer(dev, &priv_val->buf_gain);

2
drivers/media/platform/rockchip/isp/isp_params_v3x.c
View File

@@ -4081,7 +4081,7 @@ void __isp_isr_meas_en(struct rkisp_isp_params_vdev *params_vdev,
}
static
void rkisp_params_cfgsram_v3x(struct rkisp_isp_params_vdev *params_vdev)
void rkisp_params_cfgsram_v3x(struct rkisp_isp_params_vdev *params_vdev, bool is_reset)
{
struct isp3x_isp_params_cfg *params = params_vdev->isp3x_params;

34
drivers/media/platform/rockchip/isp/isp_stats_v39.c
View File

@@ -71,10 +71,7 @@ rkisp_stats_get_dhaz_stats(struct rkisp_isp_stats_vdev *stats_vdev,
dhaz->hist_iir[i][2 * j + 1] = value >> 16;
}
}
if (!dev->hw_dev->is_single) {
arg_rec->hist_iir_wr = true;
memcpy(arg_rec->hist_iir, dhaz->hist_iir, sizeof(dhaz->hist_iir));
}
memcpy(arg_rec->hist_iir, dhaz->hist_iir, sizeof(dhaz->hist_iir));
pbuf->meas_type |= ISP39_STAT_DHAZ;
}
end:
@@ -175,6 +172,9 @@ rkisp_stats_info2ddr(struct rkisp_isp_stats_vdev *stats_vdev,
int idx, buf_fd = -1;
u32 reg = 0, ctrl, mask;
if (dev->is_aiisp_en)
return;
priv_val = dev->params_vdev.priv_val;
if (!priv_val->buf_info_owner && priv_val->buf_info_idx >= 0) {
priv_val->buf_info_idx = -1;
@@ -252,24 +252,15 @@ rkisp_stats_send_meas_v39(struct rkisp_isp_stats_vdev *stats_vdev,
struct rkisp39_stat_buffer *cur_stat_buf = NULL;
u32 size = stats_vdev->vdev_fmt.fmt.meta.buffersize;
u32 cur_frame_id = meas_work->frame_id;
bool is_dummy = false;
unsigned long flags;
if (!stats_vdev->rdbk_drop) {
if (!cur_buf && stats_vdev->stats_buf[0].mem_priv) {
rkisp_finish_buffer(stats_vdev->dev, &stats_vdev->stats_buf[0]);
cur_stat_buf = stats_vdev->stats_buf[0].vaddr;
cur_stat_buf->frame_id = -1;
is_dummy = true;
} else if (cur_buf) {
if (cur_buf)
cur_stat_buf = cur_buf->vaddr[0];
}
/* buffer done when frame of right handle */
if (dev->unite_div > ISP_UNITE_DIV1) {
if (dev->unite_index == ISP_UNITE_LEFT) {
cur_buf = NULL;
is_dummy = false;
} else if (cur_stat_buf) {
cur_stat_buf = (void *)cur_stat_buf + size / dev->unite_div;
cur_stat_buf->frame_id = cur_frame_id;
@@ -313,21 +304,6 @@ rkisp_stats_send_meas_v39(struct rkisp_isp_stats_vdev *stats_vdev,
rkisp_stats_get_bay3d_stats(stats_vdev, cur_stat_buf);
}
if (is_dummy) {
spin_lock_irqsave(&stats_vdev->rd_lock, flags);
if (!list_empty(&stats_vdev->stat)) {
cur_buf = list_first_entry(&stats_vdev->stat, struct rkisp_buffer, queue);
list_del(&cur_buf->queue);
} else {
cur_stat_buf->frame_id = cur_frame_id;
cur_stat_buf->params_id = params_vdev->cur_frame_id;
}
spin_unlock_irqrestore(&stats_vdev->rd_lock, flags);
if (cur_buf) {
memcpy(cur_buf->vaddr[0], cur_stat_buf, size);
cur_stat_buf = cur_buf->vaddr[0];
}
}
if (cur_buf && cur_stat_buf) {
cur_stat_buf->frame_id = cur_frame_id;
cur_stat_buf->params_id = params_vdev->cur_frame_id;

2
drivers/media/platform/rockchip/isp/regs.c
View File

@@ -448,7 +448,7 @@ static void set_bilinear_scale(struct rkisp_stream *stream, struct v4l2_rect *in
reg = stream->config->rsz.ctrl;
rkisp_write(dev, reg, rsz_ctrl, false);
val = ISP32_SCALE_FORCE_UPD;
val = ISP32_SCALE_FORCE_UPD | ISP32_SCALE_GEN_UPD;
if (async && dev->hw_dev->is_single)
val = ISP32_SCALE_GEN_UPD;
reg = stream->config->rsz.update;

15
drivers/media/platform/rockchip/isp/rkisp.c
View File

@@ -226,8 +226,10 @@ int rkisp_align_sensor_resolution(struct rkisp_device *dev,
CIF_ISP_INPUT_H_MAX_V32_L_UNITE : CIF_ISP_INPUT_H_MAX_V32_L;
break;
case ISP_V39:
max_w = CIF_ISP_INPUT_W_MAX_V39;
max_h = CIF_ISP_INPUT_H_MAX_V39;
max_w = dev->hw_dev->unite ?
CIF_ISP_INPUT_W_MAX_V39_UNITE : CIF_ISP_INPUT_W_MAX_V39;
max_h = dev->hw_dev->unite ?
CIF_ISP_INPUT_H_MAX_V39_UNITE : CIF_ISP_INPUT_H_MAX_V39;
break;
default:
max_w = CIF_ISP_INPUT_W_MAX;
@@ -721,7 +723,7 @@ void rkisp_trigger_read_back(struct rkisp_device *dev, u8 dma2frm, u32 mode, boo
run_next:
if (!dev->sw_rd_cnt)
rkisp_rockit_frame_start(dev);
rkisp_params_cfgsram(params_vdev, true);
rkisp_params_cfgsram(params_vdev, true, false);
stats_vdev->rdbk_drop = false;
if (dev->is_frame_double) {
is_upd = true;
@@ -2746,8 +2748,10 @@ static int rkisp_isp_sd_get_selection(struct v4l2_subdev *sd,
CIF_ISP_INPUT_H_MAX_V32_L_UNITE : CIF_ISP_INPUT_H_MAX_V32_L;
break;
case ISP_V39:
max_w = CIF_ISP_INPUT_W_MAX_V39;
max_h = CIF_ISP_INPUT_H_MAX_V39;
max_w = dev->hw_dev->unite ?
CIF_ISP_INPUT_W_MAX_V39_UNITE : CIF_ISP_INPUT_W_MAX_V39;
max_h = dev->hw_dev->unite ?
CIF_ISP_INPUT_H_MAX_V39_UNITE : CIF_ISP_INPUT_H_MAX_V39;
break;
default:
max_w = CIF_ISP_INPUT_W_MAX;
@@ -4518,6 +4522,7 @@ vs_skip:
dev->isp_err_cnt = 0;
dev->isp_state &= ~ISP_ERROR;
rkisp_stream_isp_end(dev, isp_mis);
}
if (isp_mis & CIF_ISP_V_START) {