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hdmitx: modify fractional part of hpll for gxtvbb [1/1]

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PD#TV-8224

Problem:
hdmitx output clk is not right, actually output 145Mhz
when expect to output 148.5Mhz. for gxtvbb, bit[11]
of DIV_FRAC bit[11:0] is used for +/- symbol, but now
is used for fractional weight by mistake.

Solution:
change back to original setting for DIV_FRAC

Verify:
TCL-T966

Change-Id: Idd34a745d4b74a0bd9e6f2b3542af94731d5badd
Signed-off-by: Hang Cheng <hang.cheng@amlogic.com>
This commit is contained in:
Hang Cheng
2019-07-26 17:29:14 +08:00
committed by Tao Zeng
parent e86a954dee
commit cc7872eb97
1 changed files with 1 additions and 1 deletions
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2
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c
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@@ -400,7 +400,7 @@ static void set_gxtvbb_hpll_clk_out(unsigned int frac_rate, unsigned int clk)
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0x4, 28, 3);
WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL);
pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL));
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x4e00, 0, 16);
/* hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 0x4e00, 0, 16); */
break;
case 4324320:
hd_write_reg(P_HHI_HDMI_PLL_CNTL, 0x5800025a);