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clk: rockchip: rk3328: Update the h264 and h265 clocks

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fixed up the h264 and h265 clk tree change:
old:
aclk_rkvenc-->
        --> aclk_h265
        --> aclk_h264
        --> aclk_axisram
        --> hclk_rkvenc -->
       		 --> hclk_265
                 --> hclk_264
new:
sclk_venc_core-->
	--> aclk_h265
	--> aclk_h264
	--> aclk_axisram
	--> hclk_venc -->
		 --> hclk_265
		 --> hclk_264

Change-Id: I3d4b61fe545ecfc2353cb2993245fc813739084a
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang
2019-11-20 11:49:56 +08:00
parent 2fe68cb77a
commit ccf87a15a5
1 changed files with 17 additions and 16 deletions
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33
drivers/clk/rockchip/clk-rk3328.c
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@@ -547,26 +547,27 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
COMPOSITE(ACLK_RKVENC, "aclk_rkvenc", mux_4plls_p, 0,
RK3328_CLKSEL_CON(51), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3328_CLKGATE_CON(6), 3, GFLAGS),
FACTOR_GATE(HCLK_RKVENC, "hclk_rkvenc", "aclk_rkvenc", 0, 1, 4,
RK3328_CLKGATE_CON(11), 4, GFLAGS),
GATE(0, "aclk_rkvenc_niu", "aclk_rkvenc", 0,
RK3328_CLKGATE_CON(25), 0, GFLAGS),
GATE(0, "hclk_rkvenc_niu", "hclk_rkvenc", 0,
RK3328_CLKGATE_CON(25), 1, GFLAGS),
GATE(ACLK_H265, "aclk_h265", "aclk_rkvenc", 0,
RK3328_CLKGATE_CON(25), 2, GFLAGS),
GATE(PCLK_H265, "pclk_h265", "hclk_rkvenc", 0,
RK3328_CLKGATE_CON(25), 3, GFLAGS),
GATE(ACLK_H264, "aclk_h264", "aclk_rkvenc", 0,
RK3328_CLKGATE_CON(25), 4, GFLAGS),
GATE(HCLK_H264, "hclk_h264", "hclk_rkvenc", 0,
RK3328_CLKGATE_CON(25), 5, GFLAGS),
GATE(ACLK_AXISRAM, "aclk_axisram", "aclk_rkvenc", CLK_IGNORE_UNUSED,
RK3328_CLKGATE_CON(25), 6, GFLAGS),
COMPOSITE(SCLK_VENC_CORE, "sclk_venc_core", mux_4plls_p, 0,
RK3328_CLKSEL_CON(51), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3328_CLKGATE_CON(6), 4, GFLAGS),
FACTOR_GATE(0, "hclk_venc", "sclk_venc_core", 0, 1, 4,
RK3328_CLKGATE_CON(11), 4, GFLAGS),
GATE(0, "aclk_rkvenc_niu", "sclk_venc_core", 0,
RK3328_CLKGATE_CON(25), 0, GFLAGS),
GATE(0, "hclk_rkvenc_niu", "hclk_venc", 0,
RK3328_CLKGATE_CON(25), 1, GFLAGS),
GATE(ACLK_H265, "aclk_h265", "sclk_venc_core", 0,
RK3328_CLKGATE_CON(25), 2, GFLAGS),
GATE(PCLK_H265, "pclk_h265", "hclk_venc", 0,
RK3328_CLKGATE_CON(25), 3, GFLAGS),
GATE(ACLK_H264, "aclk_h264", "sclk_venc_core", 0,
RK3328_CLKGATE_CON(25), 4, GFLAGS),
GATE(HCLK_H264, "hclk_h264", "hclk_venc", 0,
RK3328_CLKGATE_CON(25), 5, GFLAGS),
GATE(ACLK_AXISRAM, "aclk_axisram", "sclk_venc_core", CLK_IGNORE_UNUSED,
RK3328_CLKGATE_CON(25), 6, GFLAGS),
COMPOSITE(SCLK_VENC_DSP, "sclk_venc_dsp", mux_4plls_p, 0,
RK3328_CLKSEL_CON(52), 14, 2, MFLAGS, 8, 5, DFLAGS,