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decoder: decrease mem use and optimize code

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PD#167435

1. decrease some mem use;
2. change vp9 4k mv buf num to 6;
3. reduce max multi-instance channels from 12 to 9;
4. avsp_long_cabac must config by option;
5. remove h264_4k2k module;
6. set_clk before init avoid timer run before work init;.
7. optimize some code in vp9/h265/avs2/mpeg2/avs.

Change-Id: Iaeedd24987649bdf04ec53e1c4c6baffb3bf1ea8
Signed-off-by: shihong.zheng <shihong.zheng@amlogic.com>
This commit is contained in:
shihong.zheng
2018-06-13 10:42:08 +08:00
committed by Dongjin Kim
parent 7088a280cc
commit cda1c484ad
9 changed files with 164 additions and 202 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/amlogic/Media.mk
View File

@@ -6,8 +6,6 @@ CONFIGS := CONFIG_AMLOGIC_MEDIA_VDEC_MPEG12=m \
CONFIG_AMLOGIC_MEDIA_VDEC_H264=m \
CONFIG_AMLOGIC_MEDIA_VDEC_H264_MULTI=m \
CONFIG_AMLOGIC_MEDIA_VDEC_H264_MVC=m \
CONFIG_AMLOGIC_MEDIA_VDEC_H264_4K2K=m \
CONFIG_AMLOGIC_MEDIA_VDEC_H264_MVC=m \
CONFIG_AMLOGIC_MEDIA_VDEC_H265=m \
CONFIG_AMLOGIC_MEDIA_VDEC_VP9=m \
CONFIG_AMLOGIC_MEDIA_VDEC_MJPEG=m \

2
drivers/amlogic/media_modules/common/firmware/firmware_drv.c
View File

@@ -45,7 +45,7 @@
#define CLASS_NAME "firmware_codec"
#define DEV_NAME "firmware_vdec"
#define DIR "video"
#define FRIMWARE_SIZE (128 * 1024) /*128k*/
#define FRIMWARE_SIZE (64 * 1024) /*64k*/
#define BUFF_SIZE (1024 * 1024 * 2)
#define FW_LOAD_FORCE (0x1)

4
drivers/amlogic/media_modules/frame_provider/decoder/avs/avs.c
View File

@@ -730,7 +730,6 @@ static int error_recovery_mode; /*0: blocky 1: mosaic*/
*static uint error_watchdog_count;
*static uint error_watchdog_buf_threshold = 0x4000000;
*/
static uint long_cabac_busy;
static struct vframe_s *vavs_vf_peek(void *op_arg)
{
@@ -1653,6 +1652,7 @@ static int amvdec_avs_probe(struct platform_device *pdev)
user_data_buffer, (u32)user_data_buffer_phys);
}
#endif
INIT_WORK(&set_clk_work, avs_set_clk);
if (vavs_init() < 0) {
pr_info("amvdec_avs init failed.\n");
kfree(gvs);
@@ -1668,7 +1668,7 @@ static int amvdec_avs_probe(struct platform_device *pdev)
INIT_WORK(&userdata_push_work, userdata_push_do_work);
#endif
INIT_WORK(&notify_work, vavs_notify_work);
INIT_WORK(&set_clk_work, avs_set_clk);
return 0;
}

2
drivers/amlogic/media_modules/frame_provider/decoder/avs/avs.h
View File

@@ -1,7 +1,9 @@
#ifndef AVS_H_
#define AVS_H_
#ifdef CONFIG_AMLOGIC_AVSP_LONG_CABAC
#define AVSP_LONG_CABAC
#endif
/*#define BITSTREAM_READ_TMP_NO_CACHE*/
#ifdef AVSP_LONG_CABAC

105
drivers/amlogic/media_modules/frame_provider/decoder/avs2/vavs2.c
View File

@@ -139,67 +139,8 @@
#define PARSER_CMD_SKIP_CFG_2 0x001b1910
#define PARSER_CMD_NUMBER 37
static unsigned short parser_cmd[PARSER_CMD_NUMBER] = {
0x0401,
0x8401,
0x0800,
0x0402,
0x9002,
0x1423,
0x8CC3,
0x1423,
0x8804,
0x9825,
0x0800,
0x04FE,
0x8406,
0x8411,
0x1800,
0x8408,
0x8409,
0x8C2A,
0x9C2B,
0x1C00,
0x840F,
0x8407,
0x8000,
0x8408,
0x2000,
0xA800,
0x8410,
0x04DE,
0x840C,
0x840D,
0xAC00,
0xA000,
0x08C0,
0x08E0,
0xA40E,
0xFC00,
0x7C00
};
static int32_t g_WqMDefault4x4[16] = {
64, 64, 64, 68,
64, 64, 68, 72,
64, 68, 76, 80,
72, 76, 84, 96
};
static int32_t g_WqMDefault8x8[64] = {
64, 64, 64, 64, 68, 68, 72, 76,
64, 64, 64, 68, 72, 76, 84, 92,
64, 64, 68, 72, 76, 80, 88, 100,
64, 68, 72, 80, 84, 92, 100, 112,
68, 72, 80, 84, 92, 104, 112, 128,
76, 80, 84, 92, 104, 116, 132, 152,
96, 100, 104, 116, 124, 140, 164, 188,
104, 108, 116, 128, 152, 172, 192, 216
};
/*#define HEVC_PIC_STRUCT_SUPPORT*/
/* to remove, fix build error */
@@ -218,7 +159,7 @@ static int32_t g_WqMDefault8x8[64] = {
#endif
#ifdef MULTI_INSTANCE_SUPPORT
#define MAX_DECODE_INSTANCE_NUM 12
#define MAX_DECODE_INSTANCE_NUM 9
#define MULTI_DRIVER_NAME "ammvdec_avs2"
#define lock_buffer(dec, flags) \
@@ -3049,6 +2990,32 @@ static void avs2_init_decoder_hw(struct AVS2Decoder_s *dec)
{
unsigned int data32;
int i;
const unsigned short parser_cmd[PARSER_CMD_NUMBER] = {
0x0401, 0x8401, 0x0800, 0x0402, 0x9002, 0x1423,
0x8CC3, 0x1423, 0x8804, 0x9825, 0x0800, 0x04FE,
0x8406, 0x8411, 0x1800, 0x8408, 0x8409, 0x8C2A,
0x9C2B, 0x1C00, 0x840F, 0x8407, 0x8000, 0x8408,
0x2000, 0xA800, 0x8410, 0x04DE, 0x840C, 0x840D,
0xAC00, 0xA000, 0x08C0, 0x08E0, 0xA40E, 0xFC00,
0x7C00
};
const int32_t g_WqMDefault4x4[16] = {
64, 64, 64, 68,
64, 64, 68, 72,
64, 68, 76, 80,
72, 76, 84, 96
};
const int32_t g_WqMDefault8x8[64] = {
64, 64, 64, 64, 68, 68, 72, 76,
64, 64, 64, 68, 72, 76, 84, 92,
64, 64, 68, 72, 76, 80, 88, 100,
64, 68, 72, 80, 84, 92, 100, 112,
68, 72, 80, 84, 92, 104, 112, 128,
76, 80, 84, 92, 104, 116, 132, 152,
96, 100, 104, 116, 124, 140, 164, 188,
104, 108, 116, 128, 152, 172, 192, 216
};
/*if (debug & AVS2_DBG_BUFMGR_MORE)
pr_info("%s\n", __func__);*/
@@ -3250,7 +3217,7 @@ static void config_avs2_clk_forced_on(void)
static struct AVS2Decoder_s gHevc;
static struct AVS2Decoder_s *gHevc;
static void avs2_local_uninit(struct AVS2Decoder_s *dec)
{
@@ -5022,11 +4989,17 @@ static int amvdec_avs2_probe(struct platform_device *pdev)
{
struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
struct BUF_s BUF[MAX_BUF_NUM];
struct AVS2Decoder_s *dec = &gHevc;
struct AVS2Decoder_s *dec;
int ret;
pr_info("%s\n", __func__);
mutex_lock(&vavs2_mutex);
dec = vmalloc(sizeof(struct AVS2Decoder_s));
if (dec == NULL) {
pr_info("failed to vamlloc amvdec_avs2 dec struct\n");
return -ENOMEM;
}
gHevc = dec;
memcpy(&BUF[0], &dec->m_BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
memset(dec, 0, sizeof(struct AVS2Decoder_s));
memcpy(&dec->m_BUF[0], &BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
@@ -5041,6 +5014,7 @@ static int amvdec_avs2_probe(struct platform_device *pdev)
if (pdata == NULL) {
avs2_print(dec, 0,
"\namvdec_avs2 memory resource undefined.\n");
vfree(dec);
mutex_unlock(&vavs2_mutex);
return -EFAULT;
}
@@ -5049,6 +5023,7 @@ static int amvdec_avs2_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, pdata);
if (amvdec_avs2_mmu_init(dec) < 0) {
vfree(dec);
mutex_unlock(&vavs2_mutex);
pr_err("avs2 alloc bmmu box failed!!\n");
return -1;
@@ -5058,6 +5033,7 @@ static int amvdec_avs2_probe(struct platform_device *pdev)
work_buf_size, DRIVER_NAME, &pdata->mem_start);
if (ret < 0) {
uninit_mmu_buffers(dec);
vfree(dec);
mutex_unlock(&vavs2_mutex);
return ret;
}
@@ -5089,6 +5065,7 @@ static int amvdec_avs2_probe(struct platform_device *pdev)
pr_info("\namvdec_avs2 init failed.\n");
avs2_local_uninit(dec);
uninit_mmu_buffers(dec);
vfree(dec);
mutex_unlock(&vavs2_mutex);
return -ENODEV;
}
@@ -5102,7 +5079,7 @@ static int amvdec_avs2_probe(struct platform_device *pdev)
static int amvdec_avs2_remove(struct platform_device *pdev)
{
struct AVS2Decoder_s *dec = &gHevc;
struct AVS2Decoder_s *dec = gHevc;
if (debug)
pr_info("amvdec_avs2_remove\n");
@@ -5119,6 +5096,8 @@ static int amvdec_avs2_remove(struct platform_device *pdev)
dec->pts_missed, dec->pts_hit, dec->frame_dur);
#endif
vfree(dec);
mutex_unlock(&vavs2_mutex);
return 0;

2
drivers/amlogic/media_modules/frame_provider/decoder/h264/Makefile
View File

@@ -4,5 +4,3 @@ amvdec_h264-objs += vh264.o
obj-$(CONFIG_AMLOGIC_MEDIA_VDEC_H264_MVC) += amvdec_h264mvc.o
amvdec_h264mvc-objs += vh264_mvc.o
obj-$(CONFIG_AMLOGIC_MEDIA_VDEC_H264_4K2K) += amvdec_h264_4k2k.o
amvdec_h264_4k2k-objs += vh264_4k2k.o

147
drivers/amlogic/media_modules/frame_provider/decoder/h265/vh265.c
View File

@@ -95,7 +95,7 @@
#endif
#ifdef MULTI_INSTANCE_SUPPORT
#define MAX_DECODE_INSTANCE_NUM 12
#define MAX_DECODE_INSTANCE_NUM 9
#define MULTI_DRIVER_NAME "ammvdec_h265"
#endif
#define DRIVER_NAME "amvdec_h265"
@@ -174,7 +174,7 @@ static unsigned int decode_timeout_val = 200;
static u32 data_resend_policy = 1;
#define VIDEO_SIGNAL_TYPE_AVAILABLE_MASK 0x20000000
/*
static const char * const video_format_names[] = {
"component", "PAL", "NTSC", "SECAM",
"MAC", "unspecified", "unspecified", "unspecified"
@@ -199,7 +199,7 @@ static const char * const matrix_coeffs_names[] = {
"fcc", "bt470bg", "smpte170m", "smpte240m",
"YCgCo", "bt2020nc", "bt2020c"
};
*/
#ifdef SUPPORT_10BIT
#define HEVC_CM_BODY_START_ADDR 0x3626
#define HEVC_CM_BODY_LENGTH 0x3627
@@ -318,7 +318,7 @@ static uint slice_parse_begin;
static u32 step;
static bool is_reset;
static u32 dynamic_buf_num_margin = 8;
static u32 dynamic_buf_num_margin = 7;
static u32 buf_alloc_width;
static u32 buf_alloc_height;
@@ -633,46 +633,6 @@ enum NalUnitType {
#define PARSER_CMD_NUMBER 37
static unsigned short parser_cmd[PARSER_CMD_NUMBER] = {
0x0401,
0x8401,
0x0800,
0x0402,
0x9002,
0x1423,
0x8CC3,
0x1423,
0x8804,
0x9825,
0x0800,
0x04FE,
0x8406,
0x8411,
0x1800,
0x8408,
0x8409,
0x8C2A,
0x9C2B,
0x1C00,
0x840F,
0x8407,
0x8000,
0x8408,
0x2000,
0xA800,
0x8410,
0x04DE,
0x840C,
0x840D,
0xAC00,
0xA000,
0x08C0,
0x08E0,
0xA40E,
0xFC00,
0x7C00
};
/**************************************************
*
*h265 buffer management
@@ -1580,6 +1540,8 @@ struct hevc_state_s {
u8 head_error_flag;
int valve_count;
struct firmware_s *fw;
int max_pic_w;
int max_pic_h;
#ifdef AGAIN_HAS_THRESHOLD
u8 next_again_flag;
u32 pre_parser_wr_ptr;
@@ -1763,16 +1725,6 @@ static int get_double_write_mode(struct hevc_state_s *hevc)
return dw;
}
/* for double write buf alloc */
static int get_double_write_mode_init(struct hevc_state_s *hevc)
{
u32 valid_dw_mode = get_valid_double_write_mode(hevc);
if (valid_dw_mode == 0x100)
return 0x1;
return valid_dw_mode;
}
static int get_double_write_ratio(struct hevc_state_s *hevc,
int dw_mode)
{
@@ -2108,12 +2060,21 @@ static int init_mmu_buffers(struct hevc_state_s *hevc)
{
int tvp_flag = vdec_secure(hw_to_vdec(hevc)) ?
CODEC_MM_FLAGS_TVP : 0;
int buf_size = 64;
if ((hevc->max_pic_w * hevc->max_pic_h) > 0 &&
(hevc->max_pic_w * hevc->max_pic_h) <= 1920*1088) {
buf_size = 24;
}
if (get_dbg_flag(hevc)) {
hevc_print(hevc, 0, "%s max_w %d max_h %d\n",
__func__, hevc->max_pic_w, hevc->max_pic_h);
}
if (hevc->mmu_enable) {
hevc->mmu_box = decoder_mmu_box_alloc_box(DRIVER_NAME,
hevc->index,
MAX_REF_PIC_NUM,
64 * SZ_1M,
buf_size * SZ_1M,
tvp_flag
);
if (!hevc->mmu_box) {
@@ -2307,7 +2268,7 @@ static int cal_current_buf_size(struct hevc_state_s *hevc,
int mc_buffer_size_h = (mc_buffer_size + 0xffff) >> 16;
int mc_buffer_size_u_v_h = 0;
int dw_mode = get_double_write_mode_init(hevc);
int dw_mode = get_double_write_mode(hevc);
if (hevc->mmu_enable)
buf_size =
@@ -2512,7 +2473,7 @@ static int config_pic(struct hevc_state_s *hevc, struct PIC_s *pic)
unsigned int y_adr = 0;
struct buf_stru_s buf_stru;
int buf_size = cal_current_buf_size(hevc, &buf_stru);
int dw_mode = get_double_write_mode_init(hevc);
int dw_mode = get_double_write_mode(hevc);
for (i = 0; i < BUF_POOL_SIZE; i++) {
if (hevc->m_BUF[i].start_adr != 0 &&
@@ -2584,7 +2545,7 @@ static void init_pic_list(struct hevc_state_s *hevc)
{
int i;
int init_buf_num = get_work_pic_num(hevc);
int dw_mode = get_double_write_mode_init(hevc);
int dw_mode = get_double_write_mode(hevc);
/*alloc decoder buf*/
for (i = 0; i < init_buf_num; i++) {
@@ -2727,7 +2688,7 @@ static void init_pic_list_hw(struct hevc_state_s *hevc)
{
int i;
int cur_pic_num = MAX_REF_PIC_NUM;
int dw_mode = get_double_write_mode_init(hevc);
int dw_mode = get_double_write_mode(hevc);
if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXL)
WRITE_VREG(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
(0x1 << 1) | (0x1 << 2));
@@ -3561,6 +3522,22 @@ static void hevc_config_work_space_hw(struct hevc_state_s *hevc)
WRITE_VREG(LMEM_DUMP_ADR, (u32)hevc->lmem_phy_addr);
}
static void parser_cmd_write(void)
{
u32 i;
const unsigned short parser_cmd[PARSER_CMD_NUMBER] = {
0x0401, 0x8401, 0x0800, 0x0402, 0x9002, 0x1423,
0x8CC3, 0x1423, 0x8804, 0x9825, 0x0800, 0x04FE,
0x8406, 0x8411, 0x1800, 0x8408, 0x8409, 0x8C2A,
0x9C2B, 0x1C00, 0x840F, 0x8407, 0x8000, 0x8408,
0x2000, 0xA800, 0x8410, 0x04DE, 0x840C, 0x840D,
0xAC00, 0xA000, 0x08C0, 0x08E0, 0xA40E, 0xFC00,
0x7C00
};
for (i = 0; i < PARSER_CMD_NUMBER; i++)
WRITE_VREG(HEVC_PARSER_CMD_WRITE, parser_cmd[i]);
}
static void hevc_init_decoder_hw(struct hevc_state_s *hevc,
int decode_pic_begin, int decode_pic_num)
{
@@ -3688,8 +3665,8 @@ static void hevc_init_decoder_hw(struct hevc_state_s *hevc,
/*WRITE_VREG(HEVC_DECODE_COUNT, 0);*/
/* Send parser_cmd */
WRITE_VREG(HEVC_PARSER_CMD_WRITE, (1 << 16) | (0 << 0));
for (i = 0; i < PARSER_CMD_NUMBER; i++)
WRITE_VREG(HEVC_PARSER_CMD_WRITE, parser_cmd[i]);
parser_cmd_write();
WRITE_VREG(HEVC_PARSER_CMD_SKIP_0, PARSER_CMD_SKIP_CFG_0);
WRITE_VREG(HEVC_PARSER_CMD_SKIP_1, PARSER_CMD_SKIP_CFG_1);
@@ -3717,7 +3694,7 @@ static void hevc_init_decoder_hw(struct hevc_state_s *hevc,
(0 << 0) /* software reset ipp and mpp */
);
if (get_double_write_mode_init(hevc) & 0x10)
if (get_double_write_mode(hevc) & 0x10)
WRITE_VREG(HEVCD_MPP_DECOMP_CTL1,
0x1 << 31 /*/Enable NV21 reference read mode for MC*/
);
@@ -3801,8 +3778,8 @@ static void decoder_hw_reset(void)
/* Send parser_cmd */
WRITE_VREG(HEVC_PARSER_CMD_WRITE, (1 << 16) | (0 << 0));
for (i = 0; i < PARSER_CMD_NUMBER; i++)
WRITE_VREG(HEVC_PARSER_CMD_WRITE, parser_cmd[i]);
parser_cmd_write();
WRITE_VREG(HEVC_PARSER_CMD_SKIP_0, PARSER_CMD_SKIP_CFG_0);
WRITE_VREG(HEVC_PARSER_CMD_SKIP_1, PARSER_CMD_SKIP_CFG_1);
@@ -5785,7 +5762,7 @@ static void release_pic_mmu_buf(struct hevc_state_s *hevc,
*
**************************************************
*/
static struct hevc_state_s gHevc;
static struct hevc_state_s *gHevc;
static void hevc_local_uninit(struct hevc_state_s *hevc)
{
@@ -7395,7 +7372,7 @@ static int hevc_recover(struct hevc_state_s *hevc)
hevc->have_valid_start_slice = 0;
if (get_double_write_mode_init(hevc) & 0x10)
if (get_double_write_mode(hevc) & 0x10)
WRITE_VREG(HEVCD_MPP_DECOMP_CTL1,
0x1 << 31 /*/Enable NV21 reference read mode for MC*/
);
@@ -8711,7 +8688,7 @@ static int h265_task_handle(void *data)
void vh265_free_cmabuf(void)
{
struct hevc_state_s *hevc = &gHevc;
struct hevc_state_s *hevc = gHevc;
mutex_lock(&vh265_mutex);
@@ -8733,7 +8710,7 @@ int vh265_dec_status(struct vdec_info *vstatus)
struct hevc_state_s *hevc =
(struct hevc_state_s *)vdec->private;
#else
struct hevc_state_s *hevc = &gHevc;
struct hevc_state_s *hevc = gHevc;
#endif
vstatus->frame_width = hevc->frame_width;
vstatus->frame_height = hevc->frame_height;
@@ -10004,8 +9981,15 @@ static int amvdec_h265_probe(struct platform_device *pdev)
struct vdec_dev_reg_s *pdata =
(struct vdec_dev_reg_s *)pdev->dev.platform_data;
#endif
struct hevc_state_s *hevc = &gHevc;
int ret;
struct hevc_state_s *hevc;
hevc = vmalloc(sizeof(struct hevc_state_s));
if (hevc == NULL) {
hevc_print(hevc, 0, "%s vmalloc hevc failed\r\n", __func__);
return -ENOMEM;
}
gHevc = hevc;
if ((debug & H265_NO_CHANG_DEBUG_FLAG_IN_CODE) == 0)
debug &= (~(H265_DEBUG_DIS_LOC_ERROR_PROC |
H265_DEBUG_DIS_SYS_ERROR_PROC));
@@ -10030,6 +10014,7 @@ static int amvdec_h265_probe(struct platform_device *pdev)
if (pdata == NULL) {
hevc_print(hevc, 0,
"\namvdec_h265 memory resource undefined.\n");
vfree(hevc);
mutex_unlock(&vh265_mutex);
return -EFAULT;
}
@@ -10043,6 +10028,7 @@ static int amvdec_h265_probe(struct platform_device *pdev)
if (init_mmu_buffers(hevc)) {
hevc_print(hevc, 0,
"\n 265 mmu init failed!\n");
vfree(hevc);
mutex_unlock(&vh265_mutex);
return -EFAULT;
}
@@ -10052,6 +10038,7 @@ static int amvdec_h265_probe(struct platform_device *pdev)
if (ret < 0) {
uninit_mmu_buffers(hevc);
devm_kfree(&pdev->dev, (void *)hevc);
vfree(hevc);
mutex_unlock(&vh265_mutex);
return ret;
}
@@ -10094,6 +10081,7 @@ static int amvdec_h265_probe(struct platform_device *pdev)
"\namvdec_h265 init failed.\n");
hevc_local_uninit(hevc);
uninit_mmu_buffers(hevc);
vfree(hevc);
mutex_unlock(&vh265_mutex);
return -ENODEV;
}
@@ -10107,7 +10095,7 @@ static int amvdec_h265_probe(struct platform_device *pdev)
static int amvdec_h265_remove(struct platform_device *pdev)
{
struct hevc_state_s *hevc = &gHevc;
struct hevc_state_s *hevc = gHevc;
if (get_dbg_flag(hevc))
hevc_print(hevc, 0, "%s\r\n", __func__);
@@ -10125,6 +10113,8 @@ static int amvdec_h265_remove(struct platform_device *pdev)
hevc->pts_missed, hevc->pts_hit, hevc->frame_dur);
#endif
vfree(hevc);
mutex_unlock(&vh265_mutex);
return 0;
@@ -10375,17 +10365,22 @@ static int ammvdec_h265_probe(struct platform_device *pdev)
/*use ptr config for doubel_write_mode, etc*/
hevc_print(hevc, 0, "pdata->config=%s\n", pdata->config);
if (get_config_int(pdata->config, "hevc_buf_margin",
&config_val) == 0)
hevc->dynamic_buf_num_margin = config_val;
else
hevc->dynamic_buf_num_margin = dynamic_buf_num_margin;
if (get_config_int(pdata->config, "hevc_double_write_mode",
&config_val) == 0)
hevc->double_write_mode = config_val;
else
hevc->double_write_mode = double_write_mode;
/*use ptr config for max_pic_w, etc*/
if (get_config_int(pdata->config, "hevc_buf_width",
&config_val) == 0) {
hevc->max_pic_w = config_val;
}
if (get_config_int(pdata->config, "hevc_buf_height",
&config_val) == 0) {
hevc->max_pic_h = config_val;
}
#endif
} else {
hevc->vh265_amstream_dec_info.width = 0;

5
drivers/amlogic/media_modules/frame_provider/decoder/mpeg12/vmpeg12.c
View File

@@ -2020,6 +2020,7 @@ static int amvdec_mpeg12_probe(struct platform_device *pdev)
vmpeg12_vdec_info_init();
INIT_WORK(&set_clk_work, vmpeg12_set_clk);
if (vmpeg12_init() < 0) {
amlog_level(LOG_LEVEL_ERROR, "amvdec_mpeg12 init failed.\n");
kfree(gvs);
@@ -2036,7 +2037,7 @@ static int amvdec_mpeg12_probe(struct platform_device *pdev)
INIT_WORK(&userdata_push_work, userdata_push_do_work);
INIT_WORK(&notify_work, vmpeg12_notify_work);
INIT_WORK(&reset_work, reset_do_work);
INIT_WORK(&set_clk_work, vmpeg12_set_clk);
last_offset = 0xFFFFFFFF;
#ifdef DUMP_USER_DATA
@@ -2168,7 +2169,7 @@ module_param(error_frame_skip_level, uint, 0664);
MODULE_PARM_DESC(error_frame_skip_level,
"\n amvdec_mpeg12 error_frame_skip_level\n");
module_param(force_first_i_ready, uint, 0664);
MODULE_PARM_DESC(dec_control, "\n amvmpeg12 force_first_i_ready\n");
MODULE_PARM_DESC(force_first_i_ready, "\n amvmpeg12 force_first_i_ready\n");
module_init(amvdec_mpeg12_driver_init_module);
module_exit(amvdec_mpeg12_driver_remove_module);

97
drivers/amlogic/media_modules/frame_provider/decoder/vp9/vvp9.c
View File

@@ -123,45 +123,6 @@
#define PARSER_CMD_NUMBER 37
unsigned short parser_cmd[PARSER_CMD_NUMBER] = {
0x0401,
0x8401,
0x0800,
0x0402,
0x9002,
0x1423,
0x8CC3,
0x1423,
0x8804,
0x9825,
0x0800,
0x04FE,
0x8406,
0x8411,
0x1800,
0x8408,
0x8409,
0x8C2A,
0x9C2B,
0x1C00,
0x840F,
0x8407,
0x8000,
0x8408,
0x2000,
0xA800,
0x8410,
0x04DE,
0x840C,
0x840D,
0xAC00,
0xA000,
0x08C0,
0x08E0,
0xA40E,
0xFC00,
0x7C00
};
/*#define HEVC_PIC_STRUCT_SUPPORT*/
/* to remove, fix build error */
@@ -181,7 +142,7 @@ unsigned short parser_cmd[PARSER_CMD_NUMBER] = {
#endif
#ifdef MULTI_INSTANCE_SUPPORT
#define MAX_DECODE_INSTANCE_NUM 12
#define MAX_DECODE_INSTANCE_NUM 9
#define MULTI_DRIVER_NAME "ammvdec_vp9"
static unsigned int max_decode_instance_num
@@ -633,6 +594,7 @@ enum REFERENCE_MODE {
#define REF_FRAMES_LOG2 3
#define REF_FRAMES (1 << REF_FRAMES_LOG2)
#define REF_FRAMES_4K (6)
/*4 scratch frames for the new frames to support a maximum of 4 cores decoding
*in parallel, 3 for scaled references on the encoder.
@@ -1191,7 +1153,7 @@ struct VP9Decoder_s {
union param_u s1_param;
u8 back_not_run_ready;
#endif
} VP9Decoder;
} ;
static void resize_context_buffers(struct VP9Decoder_s *pbi,
struct VP9_Common_s *cm, int width, int height)
@@ -1720,6 +1682,15 @@ static int init_mv_buf_list(struct VP9Decoder_s *pbi)
(~0xffff);
if (mv_buf_margin > 0)
count = REF_FRAMES + mv_buf_margin;
if (pbi->init_pic_w > 2048 && pbi->init_pic_h > 1088)
count = REF_FRAMES_4K + mv_buf_margin;
if (debug) {
pr_info("%s w:%d, h:%d, count: %d\n",
__func__, pbi->init_pic_w, pbi->init_pic_h, count);
}
for (i = 0;
i < count && i < MV_BUFFER_NUM; i++) {
if (alloc_mv_buf(pbi, i, size) < 0) {
@@ -2591,7 +2562,7 @@ int vp9_bufmgr_init(struct VP9Decoder_s *pbi, struct BuffInfo_s *buf_spec_i,
struct buff_s *mc_buf_i) {
struct VP9_Common_s *cm = &pbi->common;
/*memset(pbi, 0, sizeof(struct VP9Decoder));*/
/*memset(pbi, 0, sizeof(struct VP9Decoder_s));*/
pbi->frame_count = 0;
pbi->pic_count = 0;
pbi->pre_stream_offset = 0;
@@ -2801,7 +2772,7 @@ static u32 max_decoding_time;
static u32 error_handle_policy;
/*static u32 parser_sei_enable = 1;*/
static u32 max_buf_num = 12;
static u32 max_buf_num = 10;
static u32 run_ready_min_buf_num = 2;
@@ -5632,7 +5603,15 @@ static void vp9_init_decoder_hw(struct VP9Decoder_s *pbi, u32 mask)
{
unsigned int data32;
int i;
const unsigned short parser_cmd[PARSER_CMD_NUMBER] = {
0x0401, 0x8401, 0x0800, 0x0402, 0x9002, 0x1423,
0x8CC3, 0x1423, 0x8804, 0x9825, 0x0800, 0x04FE,
0x8406, 0x8411, 0x1800, 0x8408, 0x8409, 0x8C2A,
0x9C2B, 0x1C00, 0x840F, 0x8407, 0x8000, 0x8408,
0x2000, 0xA800, 0x8410, 0x04DE, 0x840C, 0x840D,
0xAC00, 0xA000, 0x08C0, 0x08E0, 0xA40E, 0xFC00,
0x7C00
};
#if 0
if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) {
/* Set MCR fetch priorities*/
@@ -6043,8 +6022,6 @@ static void config_mcrcc_axi_hw_new(struct VP9Decoder_s *pbi)
#endif
static struct VP9Decoder_s gHevc;
static void free_lf_buf(struct VP9Decoder_s *pbi)
{
if (pbi->lfi)
@@ -8335,11 +8312,14 @@ static int amvdec_vp9_mmu_init(struct VP9Decoder_s *pbi)
}
return 0;
}
static struct VP9Decoder_s *gHevc;
static int amvdec_vp9_probe(struct platform_device *pdev)
{
struct vdec_s *pdata = *(struct vdec_s **)pdev->dev.platform_data;
struct BUF_s BUF[MAX_BUF_NUM];
struct VP9Decoder_s *pbi = &gHevc;
struct VP9Decoder_s *pbi;
int ret;
#ifndef MULTI_INSTANCE_SUPPORT
int i;
@@ -8347,9 +8327,16 @@ static int amvdec_vp9_probe(struct platform_device *pdev)
pr_debug("%s\n", __func__);
mutex_lock(&vvp9_mutex);
pbi = vmalloc(sizeof(struct VP9Decoder_s));
if (pbi == NULL) {
pr_info("\namvdec_vp9 device data allocation failed\n");
mutex_unlock(&vvp9_mutex);
return -ENOMEM;
}
gHevc = pbi;
memcpy(&BUF[0], &pbi->m_BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
memset(pbi, 0, sizeof(VP9Decoder));
memset(pbi, 0, sizeof(struct VP9Decoder_s));
memcpy(&pbi->m_BUF[0], &BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
pbi->init_flag = 0;
@@ -8365,6 +8352,7 @@ static int amvdec_vp9_probe(struct platform_device *pdev)
pbi->show_frame_num = 0;
if (pdata == NULL) {
pr_info("\namvdec_vp9 memory resource undefined.\n");
vfree(pbi);
mutex_unlock(&vvp9_mutex);
return -EFAULT;
}
@@ -8374,6 +8362,7 @@ static int amvdec_vp9_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, pdata);
#endif
if (amvdec_vp9_mmu_init(pbi) < 0) {
vfree(pbi);
mutex_unlock(&vvp9_mutex);
pr_err("vp9 alloc bmmu box failed!!\n");
return -1;
@@ -8383,6 +8372,7 @@ static int amvdec_vp9_probe(struct platform_device *pdev)
work_buf_size, DRIVER_NAME, &pdata->mem_start);
if (ret < 0) {
uninit_mmu_buffers(pbi);
vfree(pbi);
mutex_unlock(&vvp9_mutex);
return ret;
}
@@ -8429,6 +8419,7 @@ static int amvdec_vp9_probe(struct platform_device *pdev)
pr_info("\namvdec_vp9 init failed.\n");
vp9_local_uninit(pbi);
uninit_mmu_buffers(pbi);
vfree(pbi);
mutex_unlock(&vvp9_mutex);
return -ENODEV;
}
@@ -8442,7 +8433,7 @@ static int amvdec_vp9_probe(struct platform_device *pdev)
static int amvdec_vp9_remove(struct platform_device *pdev)
{
struct VP9Decoder_s *pbi = &gHevc;
struct VP9Decoder_s *pbi = gHevc;
if (debug)
pr_info("amvdec_vp9_remove\n");
@@ -8459,7 +8450,7 @@ static int amvdec_vp9_remove(struct platform_device *pdev)
pr_info("pts missed %ld, pts hit %ld, duration %d\n",
pbi->pts_missed, pbi->pts_hit, pbi->frame_dur);
#endif
vfree(pbi);
mutex_unlock(&vvp9_mutex);
return 0;
@@ -9256,11 +9247,11 @@ static int ammvdec_vp9_probe(struct platform_device *pdev)
sizeof(struct VP9Decoder_s), GFP_KERNEL);*/
memset(&vf_dp, 0, sizeof(struct vframe_master_display_colour_s));
pbi = vmalloc(sizeof(struct VP9Decoder_s));
memset(pbi, 0, sizeof(struct VP9Decoder_s));
if (pbi == NULL) {
pr_info("\nammvdec_vp9 device data allocation failed\n");
return -ENOMEM;
}
memset(pbi, 0, sizeof(struct VP9Decoder_s));
pdata->private = pbi;
pdata->dec_status = vvp9_dec_status;
/* pdata->set_trickmode = set_trickmode; */
@@ -9271,10 +9262,8 @@ static int ammvdec_vp9_probe(struct platform_device *pdev)
pdata->threaded_irq_handler = vp9_threaded_irq_cb;
pdata->dump_state = vp9_dump_state;
memcpy(&BUF[0], &pbi->m_BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
memset(pbi, 0, sizeof(VP9Decoder));
memset(pbi, 0, sizeof(struct VP9Decoder_s));
memcpy(&pbi->m_BUF[0], &BUF[0], sizeof(struct BUF_s) * MAX_BUF_NUM);
pbi->index = pdev->id;