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ODROID-C3: clk: add a new higher cpu frequency, 2GHz for ODROID-C3

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Conflicts:
	drivers/amlogic/clk/g12a/g12a.h

Change-Id: I28496cd7d93c1ccc8770fa010e9ba6f7d2995ed6
This commit is contained in:
Joy Cho
2018-06-28 18:49:13 +09:00
committed by Chris KIM
parent 086700791a
commit cda32a36c8
2 changed files with 6 additions and 0 deletions
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4
arch/arm64/boot/dts/amlogic/s905d2_odroidc3.dts
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@@ -356,6 +356,10 @@
opp-hz = /bits/ 64 <1896000000>;
opp-microvolt = <981000>;
};
opp11 {
opp-hz = /bits/ 64 <1992000000>;
opp-microvolt = <1001000>;
};
};
cpufreq-meson {

2
drivers/amlogic/clk/g12a/g12a.h
View File

@@ -157,9 +157,11 @@ static const struct pll_rate_table g12a_pll_rate_table[] = {
PLL_RATE(1608000000ULL, 134, 1, 1), /*DCO=3216M*/
PLL_RATE(1704000000ULL, 142, 1, 1), /*DCO=3408M*/
PLL_RATE(1800000000ULL, 150, 1, 1), /*DCO=3600M*/
PLL_RATE(1872000000ULL, 156, 1, 1), /*DCO=3744M*/
PLL_RATE(1896000000ULL, 158, 1, 1), /*DCO=3792M*/
PLL_RATE(1908000000ULL, 159, 1, 1), /*DCO=3816M*/
PLL_RATE(1920000000ULL, 160, 1, 1), /*DCO=3840M*/
PLL_RATE(1992000000ULL, 166, 1, 1), /*DCO=3984M*/
PLL_RATE(2004000000ULL, 167, 1, 1), /*DCO=4008M*/
PLL_RATE(2016000000ULL, 168, 1, 1), /*DCO=4032M*/
PLL_RATE(2100000000ULL, 175, 1, 1), /*DCO=4200M*/