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phy: rockchip: mipi-dcphy: ref clock of pll cannot be 0

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Change-Id: I8add85dc269ae927a96d2ed50524e570eb60320b
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
This commit is contained in:
Guochun Huang
2024-02-19 01:34:53 +00:00
committed by Tao Huang
parent 6eeeb8ab7a
commit cdc22e20a9
1 changed files with 6 additions and 1 deletions
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7
drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
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@@ -1515,6 +1515,11 @@ samsung_mipi_dcphy_pll_round_rate(struct samsung_mipi_dcphy *samsung,
u32 min_delta = UINT_MAX;
long _dsm, best_dsm = 0;
if (!prate) {
dev_err(samsung->dev, "prate of pll can not be set zero\n");
return 0;
}
/*
* The PLL output frequency can be calculated using a simple formula:
* Fvco = ((m+k/65536) x 2 x Fin) / p
@@ -1846,7 +1851,7 @@ samsung_mipi_dcphy_pll_calc_rate(struct samsung_mipi_dcphy *samsung,
unsigned long prate = clk_get_rate(samsung->ref_clk);
unsigned long fout;
u8 scaler = 0, mfr = 0, mrr = 0;
u16 fbdiv = 1;
u16 fbdiv = 0;
u8 prediv = 1;
int dsm = 0;
int ret;