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usb code modify
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@@ -74,7 +74,7 @@
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#include "dwc_otg_cil.h"
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#include "dwc_otg_pcd.h"
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#include "dwc_otg_hcd.h"
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#include <mach/cru.h>
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//#include <mach/cru.h>
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//#define DWC_DRIVER_VERSION "2.60a 22-NOV-2006"
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//#define DWC_DRIVER_VERSION "2.70 2009-12-31"
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#define DWC_DRIVER_VERSION "3.00 2010-12-12 rockchip"
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@@ -1416,7 +1416,7 @@ static __devinit int dwc_otg_driver_probe(struct platform_device *pdev)
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dwc_otg_device->phyclk = phyclk;
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dwc_otg_device->ahbclk = ahbclk;
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#endif
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#ifdef CONFIG_ARCH_RK2928
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#if 0//def CONFIG_ARCH_RK2928
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otg_phy_con = (unsigned int*)(USBGRF_UOC0_CON5);
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cru_set_soft_reset(SOFT_RST_USBPHY0, true);
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cru_set_soft_reset(SOFT_RST_OTGC0, true);
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@@ -2176,9 +2176,6 @@ static __devinit int host20_driver_probe(struct platform_device *pdev)
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#ifdef CONFIG_ARCH_RK30
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*(unsigned int*)(USBGRF_UOC1_CON2+4) = ((1<<5)|((1<<5)<<16));
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#endif
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#ifdef CONFIG_ARCH_RK2928
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*(unsigned int*)(USBGRF_UOC1_CON5-4) = ((1<<5)|((1<<5)<<16));
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#endif
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if (dwc_otg_device == 0)
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{
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dev_err(dev, "kmalloc of dwc_otg_device failed\n");
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@@ -2311,15 +2308,6 @@ static __devinit int host20_driver_probe(struct platform_device *pdev)
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#endif
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#ifdef CONFIG_ARCH_RK30
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USB_IOMUX_INIT(GPIO0A6_HOSTDRVVBUS_NAME, GPIO0A_HOST_DRV_VBUS);
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#ifdef CONFIG_MACH_RK30_DS1001B
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USB_IOMUX_INIT(GPIO0A5_OTGDRVVBUS_NAME, GPIO0A_GPIO0A5);
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if(gpio_request(RK30_PIN0_PA5,"host_drv")<0){
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DWC_ERROR("request of host power control failed\n");
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gpio_free(RK30_PIN0_PA5);
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}
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gpio_direction_output(RK30_PIN0_PA5, GPIO_HIGH);
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gpio_set_value(RK30_PIN0_PA5, GPIO_HIGH);
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#endif
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#endif
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/*
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* Initialize the DWC_otg core.
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@@ -618,7 +618,7 @@ static int32_t dwc_otg_phy_suspend_cb( void *_p, int suspend)
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DWC_DEBUGPL(DBG_PCDV, "disable usb phy\n");
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}
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#endif
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#ifdef CONFIG_ARCH_RK2928
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#if 0//def CONFIG_ARCH_RK2928
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unsigned int * otg_phy_con1 = (unsigned int*)(USBGRF_UOC0_CON5);
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if(exitsuspend && (pcd->phy_suspend == 1)) {
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clk_enable(pcd->otg_dev->ahbclk);
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@@ -1143,7 +1143,7 @@ static int32_t host20_phy_suspend_cb( void *_p, int suspend)
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DWC_DEBUGPL(DBG_PCDV, "disable usb phy\n");
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}
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#endif
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#ifdef CONFIG_ARCH_RK2928
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#if 0//def CONFIG_ARCH_RK2928
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unsigned int * otg_phy_con1 = (unsigned int*)(USBGRF_UOC0_CON5);
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if(exitsuspend && (pcd->phy_suspend == 1)) {
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clk_enable(pcd->otg_dev->ahbclk);
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@@ -1604,6 +1604,7 @@ int dwc_pcd_reset(dwc_otg_pcd_t *pcd)
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cru_set_soft_reset(SOFT_RST_USB_OTG_2_0_AHB_BUS, false);
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cru_set_soft_reset(SOFT_RST_USB_OTG_2_0_PHY, false);
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cru_set_soft_reset(SOFT_RST_USB_OTG_2_0_CONTROLLER, false);
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mdelay(1);
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#endif
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//rockchip_scu_reset_unit(12);
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dwc_otg_pcd_reinit( pcd );
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