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irblaster: code optimization for axg g12a and g12b

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PD#172603: irblaster: code optimization

Add interrupt for irblaster. Because it adds a way to
interrupt starting with axg. Check out AO_IR_BLASTER_ADDR3
for details.

Change-Id: I24761207d43c1d783a4669b352f2f93e994df357
Signed-off-by: Yu Tu <yu.tu@amlogic.com>
This commit is contained in:
Yu Tu
2018-09-07 17:55:08 +08:00
parent 7c7d0fe3e5
commit ce60ab4bd6
14 changed files with 484 additions and 554 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
arch/arm64/boot/dts/amlogic/axg_a113x_skt.dts
View File

@@ -316,14 +316,6 @@
pinctrl-0 = <&b_uart_pins>;
};
meson-irblaster {
compatible = "amlogic, am_irblaster";
dev_name = "meson-irblaster";
status = "disable";
pinctrl-names = "default";
pinctrl-0 = <&irblaster_pins>;
};
/* Sound iomap */
aml_snd_iomap {
compatible = "amlogic, snd-iomap";

8
arch/arm64/boot/dts/amlogic/axg_s400.dts
View File

@@ -425,14 +425,6 @@
pinctrl-0 = <&b_uart_pins>;
};
meson-irblaster {
compatible = "amlogic, am_irblaster";
dev_name = "meson-irblaster";
status = "disable";
pinctrl-names = "default";
pinctrl-0 = <&irblaster_pins>;
};
vpu {
compatible = "amlogic, vpu-axg";
dev_name = "vpu";

8
arch/arm64/boot/dts/amlogic/axg_s400_v03.dts
View File

@@ -425,14 +425,6 @@
pinctrl-0 = <&b_uart_pins>;
};
meson-irblaster {
compatible = "amlogic, am_irblaster";
dev_name = "meson-irblaster";
status = "disable";
pinctrl-names = "default";
pinctrl-0 = <&irblaster_pins>;
};
vpu {
compatible = "amlogic, vpu-axg";
dev_name = "vpu";

8
arch/arm64/boot/dts/amlogic/axg_s400emmc.dts
View File

@@ -413,14 +413,6 @@
pinctrl-0 = <&b_uart_pins>;
};
meson-irblaster {
compatible = "amlogic, am_irblaster";
dev_name = "meson-irblaster";
status = "disable";
pinctrl-names = "default";
pinctrl-0 = <&irblaster_pins>;
};
vpu {
compatible = "amlogic, vpu-axg";
dev_name = "vpu";

8
arch/arm64/boot/dts/amlogic/axg_s400emmc_512m.dts
View File

@@ -434,14 +434,6 @@
pinctrl-0 = <&b_uart_pins>;
};
meson-irblaster {
compatible = "amlogic, am_irblaster";
dev_name = "meson-irblaster";
status = "disable";
pinctrl-names = "default";
pinctrl-0 = <&irblaster_pins>;
};
vpu {
compatible = "amlogic, vpu-axg";
dev_name = "vpu";

8
arch/arm64/boot/dts/amlogic/axg_s400emmc_v03.dts
View File

@@ -421,14 +421,6 @@
pinctrl-0 = <&b_uart_pins>;
};
meson-irblaster {
compatible = "amlogic, am_irblaster";
dev_name = "meson-irblaster";
status = "disable";
pinctrl-names = "default";
pinctrl-0 = <&irblaster_pins>;
};
vpu {
compatible = "amlogic, vpu-axg";
dev_name = "vpu";

8
arch/arm64/boot/dts/amlogic/axg_s420.dts
View File

@@ -320,14 +320,6 @@
pinctrl-0 = <&b_uart_pins>;
};
meson-irblaster {
compatible = "amlogic, am_irblaster";
dev_name = "meson-irblaster";
status = "disable";
pinctrl-names = "default";
pinctrl-0 = <&irblaster_pins>;
};
/* Sound iomap */
aml_snd_iomap {
compatible = "amlogic, snd-iomap";

8
arch/arm64/boot/dts/amlogic/axg_s420_128m.dts
View File

@@ -309,14 +309,6 @@
pinctrl-0 = <&b_uart_pins>;
};
meson-irblaster {
compatible = "amlogic, am_irblaster";
dev_name = "meson-irblaster";
status = "disable";
pinctrl-names = "default";
pinctrl-0 = <&irblaster_pins>;
};
/* Sound iomap */
aml_snd_iomap {
compatible = "amlogic, snd-iomap";

8
arch/arm64/boot/dts/amlogic/axg_s420_v03.dts
View File

@@ -320,14 +320,6 @@
pinctrl-0 = <&b_uart_pins>;
};
meson-irblaster {
compatible = "amlogic, am_irblaster";
dev_name = "meson-irblaster";
status = "disable";
pinctrl-names = "default";
pinctrl-0 = <&irblaster_pins>;
};
/* Sound iomap */
aml_snd_iomap {
compatible = "amlogic, snd-iomap";

10
arch/arm64/boot/dts/amlogic/mesonaxg.dtsi
View File

@@ -738,6 +738,16 @@
};
};
irblaster: meson-irblaster {
compatible = "amlogic, meson_irblaster";
reg = <0x0 0xff8000c0 0x0 0x10>,
<0x0 0xff800040 0x0 0x4>;
pinctrl-names = "default";
pinctrl-0 = <&irblaster_pins>;
interrupts = <0 198 1>;
status = "disabled";
};
saradc:saradc {
compatible = "amlogic,meson-axg-saradc";
status = "okay";

2
arch/arm64/boot/dts/amlogic/mesong12a.dtsi
View File

@@ -1324,11 +1324,11 @@
};
irblaster: meson-irblaster {
compatible = "amlogic, meson_irblaster";
dev_name = "meson-irblaster";
reg = <0x0 0xff80014c 0x0 0x10>,
<0x0 0xff800040 0x0 0x4>;
pinctrl-names = "default";
pinctrl-0 = <&irblaster_pins>;
interrupts = <0 198 1>;
status = "okay";
};

4
arch/arm64/boot/dts/amlogic/mesong12b.dtsi
View File

@@ -1371,12 +1371,12 @@
};
irblaster: meson-irblaster {
compatible = "amlogic, meson_irblaster";
dev_name = "meson-irblaster";
reg = <0x0 0xff80014c 0x0 0x10>,
<0x0 0xff800040 0x0 0x4>;
pinctrl-names = "default";
pinctrl-0 = <&irblaster_pins>;
status = "okay";
interrupts = <0 198 1>;
status = "disabled";
};
sd_emmc_c: emmc@ffe07000 {

875
drivers/amlogic/irblaster/meson-irblaster.c
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File diff suppressed because it is too large Load Diff

75
drivers/amlogic/irblaster/meson-irblaster.h
View File

@@ -15,21 +15,78 @@
*
*/
#ifndef AM_IRBLASTER_H
#define AM_IRBLASTER_H
#define MAX_PLUSE 1024
#ifndef __LINUX_AML_IR_BLASTER_H
#define __LINUX_AML_IR_BLASTER_H
/* Amlogic AO_IR_BLASTER_ADDR0 bits */
#define BLASTER_BUSY BIT(26)
#define BLASTER_FIFO_FULL BIT(25)
#define BLASTER_FIFO_EMPTY BIT(24)
#define BLASTER_FIFO_LEVEL (0xff << 16)
#define BLASTER_MODULATOR_TB_SYSTEM_CLOCK (0x0 << 12)
#define BLASTER_MODULATOR_TB_XTAL3_TICK (0x1 << 12)
#define BLASTER_MODULATOR_TB_1US_TICK (0x2 << 12)
#define BLASTER_MODULATOR_TB_10US_TICK (0x3 << 12)
#define BLASTER_SLOW_CLOCK_DIV (0xff << 4)
#define BLASTER_SLOW_CLOCK_MODE BIT(3)
#define BLASTER_INIT_HIGH BIT(2)
#define BLASTER_INIT_LOW BIT(1)
#define BLASTER_ENABLE BIT(0)
/* Amlogic AO_IR_BLASTER_ADDR1 bits */
#define BLASTER_MODULATION_LOW_COUNT(c) ((c) << 16)
#define BLASTER_MODULATION_HIGH_COUNT(c) ((c) << 0)
/* Amlogic AO_IR_BLASTER_ADDR2 bits */
#define BLASTER_WRITE_FIFO BIT(16)
#define BLASTER_MODULATION_ENABLE BIT(12)
#define BLASTER_TIMEBASE_1US (0x0 << 10)
#define BLASTER_TIMEBASE_10US (0x1 << 10)
#define BLASTER_TIMEBASE_100US (0x2 << 10)
#define BLASTER_TIMEBASE_MODULATION_CLOCK (0x3 << 10)
/* Amlogic AO_IR_BLASTER_ADDR3 bits */
#define BLASTER_FIFO_THD_PENDING BIT(16)
#define BLASTER_FIFO_IRQ_ENABLE BIT(8)
#define BLASTER_FIFO_IRQ_THRESHOLD(c) (((c) & 0xff) << 0)
#define DEFAULT_CARRIER_FREQ (38000)
#define DEFAULT_DUTY_CYCLE (50)
#define BLASTER_DEVICE_COUNT (32)
#define MAX_PLUSE (1024)
#define PS_SIZE (10)
#define LIMIT_DUTY (25)
#define MAX_DUTY (75)
#define LIMIT_FREQ (25000)
#define MAX_FREQ (60000)
#define COUNT_DELAY_MASK (0X3ff)
#define TIMEBASE_SHIFT (10)
#define BLASTER_KFIFO_SIZE (4)
enum { /* Modulation level*/
fisrt_low = 0,
fisrt_high = 1
};
struct blaster_window {
unsigned int winnum;
unsigned int winarray[MAX_PLUSE];
int consumerir_freqs;
unsigned int consumerir_dutycycle;
struct mutex lock;
struct blaster_kfifo {
int size;
unsigned int buffer[MAX_PLUSE];
};
struct aml_irblaster_dev {
struct device *dev;
struct work_struct blaster_work;
struct class *blaster_class;
struct cdev blaster_cdev;
unsigned int count;
unsigned int irq;
unsigned int buffer_size;
unsigned int buffer[MAX_PLUSE];
unsigned int carrier_freqs;
unsigned int duty_cycle;
struct completion blaster_completion;
void __iomem *reg_base;
void __iomem *reset_base;
};