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hdmitx: update phy setting of 3G for SM1 [2/2]

Browse Source 
PD#SWPL-8791

Problem:
HDMITX Eye Diagram of SM1 test fail

Solution:
Optimize the PHY setting.

Verify:
SM1

Change-Id: I33d8b8a1a515fe478845287c44271524b256c5f1
Signed-off-by: yicheng shen <yicheng.shen@amlogic.com>
Signed-off-by: Luan Yuan <luan.yuan@amlogic.com>
This commit is contained in:
yicheng shen
2019-06-24 16:00:05 +08:00
committed by Chris KIM
parent ca5cb7d0df
commit ceb6a6c693
2 changed files with 21 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

21
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c
View File

@@ -1997,7 +1997,6 @@ static void set_phy_by_mode(unsigned int mode)
switch (hdev->chip_type) {
case MESON_CPU_ID_G12A:
case MESON_CPU_ID_G12B:
case MESON_CPU_ID_SM1:
switch (mode) {
case 1: /* 5.94/4.5/3.7Gbps */
hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x37eb65c4);
@@ -2017,6 +2016,26 @@ static void set_phy_by_mode(unsigned int mode)
break;
}
break;
case MESON_CPU_ID_SM1:
switch (mode) {
case 1: /* 5.94/4.5/3.7Gbps */
hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x37eb65c4);
hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x0000080b);
break;
case 2: /* 2.97Gbps */
hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x33eb42a2);
hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x00000003);
break;
case 3: /* 1.485Gbps, and below */
default:
hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x33eb4242);
hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x00000003);
break;
}
break;
case MESON_CPU_ID_M8B:
case MESON_CPU_ID_GXBB:
case MESON_CPU_ID_GXTVBB:

2
include/linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h
View File

@@ -27,7 +27,7 @@
#include <linux/pinctrl/consumer.h>
/* HDMITX driver version */
#define HDMITX_VER "20181019"
#define HDMITX_VER "20190624"
/* chip type */
#define MESON_CPU_ID_M8B 0