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arm64: dts: rockchip: rk3528: Set default value with level2 for spi

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Change-Id: I7f14eb9438998660b85f09fb11f7006be420c4e1
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
This commit is contained in:
Jon Lin
2023-08-15 10:46:24 +08:00
committed by Tao Huang
parent 83cd5cd9b4
commit cf0f63fbfc
1 changed files with 10 additions and 10 deletions
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20
arch/arm64/boot/dts/rockchip/rk3528-pinctrl.dtsi
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@@ -1030,24 +1030,24 @@
spi0_pins: spi0-pins {
rockchip,pins =
/* spi0_clk */
<4 RK_PB4 2 &pcfg_pull_none>,
<4 RK_PB4 2 &pcfg_pull_none_drv_level_2>,
/* spi0_miso */
<4 RK_PB3 2 &pcfg_pull_none>,
<4 RK_PB3 2 &pcfg_pull_none_drv_level_2>,
/* spi0_mosi */
<4 RK_PB2 2 &pcfg_pull_none>;
<4 RK_PB2 2 &pcfg_pull_none_drv_level_2>;
};
/omit-if-no-ref/
spi0_csn0: spi0-csn0 {
rockchip,pins =
/* spi0_csn0 */
<4 RK_PB6 2 &pcfg_pull_none>;
<4 RK_PB6 2 &pcfg_pull_none_drv_level_2>;
};
/omit-if-no-ref/
spi0_csn1: spi0-csn1 {
rockchip,pins =
/* spi0_csn1 */
<4 RK_PC1 2 &pcfg_pull_none>;
<4 RK_PC1 2 &pcfg_pull_none_drv_level_2>;
};
};
@@ -1056,24 +1056,24 @@
spi1_pins: spi1-pins {
rockchip,pins =
/* spi1_clk */
<1 RK_PB6 2 &pcfg_pull_none>,
<1 RK_PB6 2 &pcfg_pull_none_drv_level_2>,
/* spi1_miso */
<1 RK_PC0 2 &pcfg_pull_none>,
<1 RK_PC0 2 &pcfg_pull_none_drv_level_2>,
/* spi1_mosi */
<1 RK_PB7 2 &pcfg_pull_none>;
<1 RK_PB7 2 &pcfg_pull_none_drv_level_2>;
};
/omit-if-no-ref/
spi1_csn0: spi1-csn0 {
rockchip,pins =
/* spi1_csn0 */
<1 RK_PC1 1 &pcfg_pull_none>;
<1 RK_PC1 1 &pcfg_pull_none_drv_level_2>;
};
/omit-if-no-ref/
spi1_csn1: spi1-csn1 {
rockchip,pins =
/* spi1_csn1 */
<1 RK_PC2 1 &pcfg_pull_none>;
<1 RK_PC2 1 &pcfg_pull_none_drv_level_2>;
};
};