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clock: G12A: fine-tune pcie/common pll parameters

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PD#156734: clock: G12A: fine-tune pcie/common pll parameters

Change-Id: Ifbd8d07928deeebaa35c4f950efc290b1648394e
Signed-off-by: Qiufang Dai <qiufang.dai@amlogic.com>
This commit is contained in:
Qiufang Dai
2018-01-31 17:53:16 +08:00
committed by Yixun Lan
parent b0d6e0a082
commit cf13cbd5a0
3 changed files with 30 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/amlogic/clk/clkc.h
View File

@@ -214,6 +214,7 @@ extern const struct clk_ops meson_axg_pll_ro_ops;
extern const struct clk_ops meson_axg_pll_ops;
extern const struct clk_ops meson_g12a_pll_ro_ops;
extern const struct clk_ops meson_g12a_pll_ops;
extern const struct clk_ops meson_g12a_pcie_pll_ops;
extern const struct clk_ops meson_g12a_mpll_ro_ops;
extern const struct clk_ops meson_g12a_mpll_ops;

2
drivers/amlogic/clk/g12a/g12a.c
View File

@@ -186,7 +186,7 @@ static struct meson_clk_pll g12a_pcie_pll = {
.lock = &clk_lock,
.hw.init = &(struct clk_init_data){
.name = "pcie_pll",
.ops = &meson_g12a_pll_ops,
.ops = &meson_g12a_pcie_pll_ops,
.parent_names = (const char *[]){ "xtal" },
.num_parents = 1,
.flags = CLK_GET_RATE_NOCACHE,

46
drivers/amlogic/clk/g12a/g12a_clk-pll.c
View File

@@ -51,8 +51,13 @@
/* G12A */
//#define G12A_PCIE_PLL_CNTL 0x400106c8
#define G12A_PCIE_PLL_CNTL0_0 0x200c04c8
#define G12A_PCIE_PLL_CNTL0_1 0x300c04c8
#define G12A_PCIE_PLL_CNTL0_2 0x340c04c8
#define G12A_PCIE_PLL_CNTL0_3 0x140c04c8
#define G12A_PCIE_PLL_CNTL1 0x00000000
#define G12A_PCIE_PLL_CNTL2 0x00001000
#define G12A_PCIE_PLL_CNTL2 0x00001100
#define G12A_PCIE_PLL_CNTL2_ 0x00001000
#define G12A_PCIE_PLL_CNTL3 0x10058e00
#define G12A_PCIE_PLL_CNTL4 0x000100c0
#define G12A_PCIE_PLL_CNTL4_ 0x008100c0
@@ -61,8 +66,8 @@
#define G12A_PLL_CNTL1 0x00000000
#define G12A_PLL_CNTL2 0x00000000
#define G12A_PLL_CNTL3 0x0a691c20
#define G12A_PLL_CNTL4 0x33071290
#define G12A_PLL_CNTL3 0x0a691c00
#define G12A_PLL_CNTL4 0x33771290
#define G12A_PLL_CNTL5 0x39270000
#define G12A_PLL_CNTL6 0x50540000
@@ -213,10 +218,9 @@ static int meson_g12a_pll_set_rate(struct clk_hw *hw, unsigned long rate,
|| !strcmp(clk_hw_get_name(hw), "sys_pll")) {
void *cntlbase = pll->base + p->reg_off;
writel((readl(cntlbase) | MESON_PLL_RESET)
& (~MESON_PLL_ENABLE), cntlbase);
if (!strcmp(clk_hw_get_name(hw), "pcie_pll")) {
writel(G12A_PCIE_PLL_CNTL0_0, cntlbase + (u64)(0*4));
writel(G12A_PCIE_PLL_CNTL0_1, cntlbase + (u64)(0*4));
writel(G12A_PCIE_PLL_CNTL1, cntlbase + (u64)(1*4));
writel(G12A_PCIE_PLL_CNTL2, cntlbase + (u64)(2*4));
writel(G12A_PCIE_PLL_CNTL3, cntlbase + (u64)(3*4));
@@ -227,9 +231,14 @@ static int meson_g12a_pll_set_rate(struct clk_hw *hw, unsigned long rate,
writel(G12A_PCIE_PLL_CNTL4_, cntlbase + (u64)(4*4));
udelay(10);
/*set pcie_apll_afc_start bit*/
writel(readl(cntlbase) | (1 << 26), cntlbase);
writel(G12A_PCIE_PLL_CNTL0_2, cntlbase + (u64)(0*4));
writel(G12A_PCIE_PLL_CNTL0_3, cntlbase + (u64)(0*4));
udelay(10);
writel(G12A_PCIE_PLL_CNTL2_, cntlbase + (u64)(2*4));
goto OUT;
} else {
writel((readl(cntlbase) | MESON_PLL_RESET)
& (~MESON_PLL_ENABLE), cntlbase);
writel(G12A_PLL_CNTL1, cntlbase + (u64)1*4);
writel(G12A_PLL_CNTL2, cntlbase + (u64)2*4);
writel(G12A_PLL_CNTL3, cntlbase + (u64)3*4);
@@ -363,19 +372,14 @@ static void meson_g12a_pll_disable(struct clk_hw *hw)
struct parm *p = &pll->n;
unsigned long flags = 0;
if (!strcmp(clk_hw_get_name(hw), "gp0_pll")
|| !strcmp(clk_hw_get_name(hw), "hifi_pll")
|| !strcmp(clk_hw_get_name(hw), "pcie_pll")) {
if (pll->lock)
spin_lock_irqsave(pll->lock, flags);
if (pll->lock)
spin_lock_irqsave(pll->lock, flags);
writel(readl(pll->base + p->reg_off) & (~MESON_PLL_ENABLE),
pll->base + p->reg_off);
if (pll->lock)
spin_unlock_irqrestore(pll->lock, flags);
}
writel(readl(pll->base + p->reg_off) & (~MESON_PLL_ENABLE),
pll->base + p->reg_off);
if (pll->lock)
spin_unlock_irqrestore(pll->lock, flags);
}
const struct clk_ops meson_g12a_pll_ops = {
@@ -386,6 +390,12 @@ const struct clk_ops meson_g12a_pll_ops = {
.disable = meson_g12a_pll_disable,
};
const struct clk_ops meson_g12a_pcie_pll_ops = {
.recalc_rate = meson_g12a_pll_recalc_rate,
.enable = meson_g12a_pll_enable,
.disable = meson_g12a_pll_disable,
};
const struct clk_ops meson_g12a_pll_ro_ops = {
.recalc_rate = meson_g12a_pll_recalc_rate,
};