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ethernet: add interface to delay rx/tx clk [1/1]

Browse Source 
PD#SWPL-9720

Problem:
difference window area between chips

Solution:
add interface to custom

Verify:
verify on g12a u200 board

Change-Id: I589c890e36961f533bffae557337b24a09f1bf41
Signed-off-by: Zhuo Wang <zhuo.wang@amlogic.com>
This commit is contained in:
Zhuo Wang
2019-06-12 16:07:22 +08:00
committed by Chris KIM
parent a58c52f1b7
commit cf1ca1b5bb
3 changed files with 22 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c
View File

@@ -376,6 +376,10 @@ static void __iomem *g12a_network_interface_setup(struct platform_device *pdev)
/*config extern phy*/
if (internal_phy == 0) {
if (of_property_read_u32(np, "tx_delay", &external_tx_delay))
pr_debug("set exphy tx delay\n");
if (of_property_read_u32(np, "rx_delay", &external_rx_delay))
pr_debug("set exphy rx delay\n");
/* only exphy support wol since g12a*/
/*we enable/disable wol with item in dts with "wol=<1>"*/
if (of_property_read_u32(np, "wol",

3
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.h
View File

@@ -33,6 +33,8 @@ int stmmac_pltfr_remove(struct platform_device *pdev);
#ifdef CONFIG_AMLOGIC_ETH_PRIVE
int stmmac_pltfr_suspend(struct device *dev);
int stmmac_pltfr_resume(struct device *dev);
extern unsigned int external_rx_delay;
extern unsigned int external_tx_delay;
#endif
extern const struct dev_pm_ops stmmac_pltfr_pm_ops;
@@ -43,5 +45,4 @@ static inline void *get_stmmac_bsp_priv(struct device *dev)
return priv->plat->bsp_priv;
}
#endif /* __STMMAC_PLATFORM_H__ */

16
drivers/net/phy/realtek.c
View File

@@ -45,6 +45,8 @@ MODULE_LICENSE("GPL");
#ifdef CONFIG_AMLOGIC_ETH_PRIVE
unsigned int support_external_phy_wol;
unsigned int external_rx_delay;
unsigned int external_tx_delay;
#endif
static int rtl821x_ack_interrupt(struct phy_device *phydev)
{
@@ -130,6 +132,20 @@ static int rtl8211f_config_init(struct phy_device *phydev)
phy_write(phydev, 0x11, reg);
#ifdef CONFIG_AMLOGIC_ETH_PRIVE
if (external_rx_delay) {
/*add 2ns delay for rx*/
phy_write(phydev, RTL8211F_PAGE_SELECT, 0xd08);
reg = phy_read(phydev, 0x15);
reg = phy_write(phydev, 0x15, reg | 0x8);
phy_write(phydev, RTL8211F_PAGE_SELECT, 0x0);
}
if (external_tx_delay) {
/*add 2ns delay for tx*/
phy_write(phydev, RTL8211F_PAGE_SELECT, 0xd08);
reg = phy_read(phydev, 0x11);
reg = phy_write(phydev, 0x11, reg | 0x100);
phy_write(phydev, RTL8211F_PAGE_SELECT, 0x0);
}
/*disable clk_out pin 35 set page 0x0a43 reg25.0 as 0*/
phy_write(phydev, RTL8211F_PAGE_SELECT, 0x0a43);
reg = phy_read(phydev, 0x19);