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ASoC: rk3308_codec: fix the incorrect description for ADC1/ADC2

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From the broken spec from vendor, the PGA GAIN description
for MIC-IN should be like this:
 * 0x0 - MIC1~MIC8 0dB
 * 0x1 - MIC1~MIC2 are invalid, MIC3~MIC8 6.6dB
 * 0x2 - MIC1~MIC2 are invalid, MIC3~MIC8 13dB
 * 0x3 - MIC1~MIC8 20dB

Therefore, we need to update the MIC-INs dapm controls:

- MIC1 / MIC2:
numid=25,iface=MIXER,name='ADC MIC Group 0 Left Volume'
  ; type=INTEGER,access=rw---R--,values=1,min=0,max=3,step=0
  : values=0
  | dBrange-
    rangemin=0,,rangemax=0
      | dBminmax-min=0.00dB,max=0.00dB
    rangemin=3,,rangemax=3
      | dBminmax-min=20.00dB,max=20.00dB

- MIC3 ~ MIC8:
numid=27,iface=MIXER,name='ADC MIC Group 1 Left Volume'
  ; type=INTEGER,access=rw---R--,values=1,min=0,max=3,step=0
  : values=0
  | dBrange-
    rangemin=0,,rangemax=0
      | dBminmax-min=0.00dB,max=0.00dB
    rangemin=1,,rangemax=1
      | dBminmax-min=6.60dB,max=6.60dB
    rangemin=2,,rangemax=2
      | dBminmax-min=13.00dB,max=13.00dB
    rangemin=3,,rangemax=3
      | dBminmax-min=20.00dB,max=20.00dB

Change-Id: I977179fdf33d6bb7e27708baef37cc308c3d0a71
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
This commit is contained in:
Xing Zheng
2018-04-28 19:52:43 +08:00
committed by Tao Huang
parent 686e6dfc50
commit cfb4b8e9b2
2 changed files with 33 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files

28
sound/soc/codecs/rk3308_codec.c
View File

@@ -107,8 +107,6 @@ static const DECLARE_TLV_DB_SCALE(rk3308_codec_alc_agc_grp_max_gain_tlv,
-1350, 600, 2850);
static const DECLARE_TLV_DB_SCALE(rk3308_codec_alc_agc_grp_min_gain_tlv,
-1800, 600, 2400);
static const DECLARE_TLV_DB_SCALE(rk3308_codec_adc_mic_gain_tlv,
0, 600, 3000);
static const DECLARE_TLV_DB_SCALE(rk3308_codec_adc_alc_gain_tlv,
-1800, 150, 2850);
static const DECLARE_TLV_DB_SCALE(rk3308_codec_dac_lineout_gain_tlv,
@@ -117,6 +115,16 @@ static const DECLARE_TLV_DB_SCALE(rk3308_codec_dac_hpout_gain_tlv,
-3900, 150, 600);
static const DECLARE_TLV_DB_SCALE(rk3308_codec_dac_hpmix_gain_tlv,
-600, 600, 0);
static const DECLARE_TLV_DB_RANGE(rk3308_codec_adc_1_2_mic_gain_tlv,
0, 0, TLV_DB_MINMAX_ITEM(0, 0),
3, 3, TLV_DB_MINMAX_ITEM(2000, 2000),
);
static const DECLARE_TLV_DB_RANGE(rk3308_codec_adc_3_8_mic_gain_tlv,
0, 0, TLV_DB_MINMAX_ITEM(0, 0),
1, 1, TLV_DB_MINMAX_ITEM(660, 660),
2, 2, TLV_DB_MINMAX_ITEM(1300, 1300),
3, 3, TLV_DB_MINMAX_ITEM(2000, 2000),
);
static const struct snd_kcontrol_new rk3308_codec_dapm_controls[] = {
/* ALC AGC Group */
@@ -284,49 +292,49 @@ static const struct snd_kcontrol_new rk3308_codec_dapm_controls[] = {
RK3308_ADC_CH1_MIC_GAIN_SFT,
RK3308_ADC_CH1_MIC_GAIN_MIN,
RK3308_ADC_CH1_MIC_GAIN_MAX,
0, rk3308_codec_adc_mic_gain_tlv),
0, rk3308_codec_adc_1_2_mic_gain_tlv),
SOC_SINGLE_RANGE_TLV("ADC MIC Group 0 Right Volume",
RK3308_ADC_ANA_CON01(0),
RK3308_ADC_CH2_MIC_GAIN_SFT,
RK3308_ADC_CH2_MIC_GAIN_MIN,
RK3308_ADC_CH2_MIC_GAIN_MAX,
0, rk3308_codec_adc_mic_gain_tlv),
0, rk3308_codec_adc_1_2_mic_gain_tlv),
SOC_SINGLE_RANGE_TLV("ADC MIC Group 1 Left Volume",
RK3308_ADC_ANA_CON01(1),
RK3308_ADC_CH1_MIC_GAIN_SFT,
RK3308_ADC_CH1_MIC_GAIN_MIN,
RK3308_ADC_CH1_MIC_GAIN_MAX,
0, rk3308_codec_adc_mic_gain_tlv),
0, rk3308_codec_adc_3_8_mic_gain_tlv),
SOC_SINGLE_RANGE_TLV("ADC MIC Group 1 Right Volume",
RK3308_ADC_ANA_CON01(1),
RK3308_ADC_CH2_MIC_GAIN_SFT,
RK3308_ADC_CH2_MIC_GAIN_MIN,
RK3308_ADC_CH2_MIC_GAIN_MAX,
0, rk3308_codec_adc_mic_gain_tlv),
0, rk3308_codec_adc_3_8_mic_gain_tlv),
SOC_SINGLE_RANGE_TLV("ADC MIC Group 2 Left Volume",
RK3308_ADC_ANA_CON01(2),
RK3308_ADC_CH1_MIC_GAIN_SFT,
RK3308_ADC_CH1_MIC_GAIN_MIN,
RK3308_ADC_CH1_MIC_GAIN_MAX,
0, rk3308_codec_adc_mic_gain_tlv),
0, rk3308_codec_adc_3_8_mic_gain_tlv),
SOC_SINGLE_RANGE_TLV("ADC MIC Group 2 Right Volume",
RK3308_ADC_ANA_CON01(2),
RK3308_ADC_CH2_MIC_GAIN_SFT,
RK3308_ADC_CH2_MIC_GAIN_MIN,
RK3308_ADC_CH2_MIC_GAIN_MAX,
0, rk3308_codec_adc_mic_gain_tlv),
0, rk3308_codec_adc_3_8_mic_gain_tlv),
SOC_SINGLE_RANGE_TLV("ADC MIC Group 3 Left Volume",
RK3308_ADC_ANA_CON01(3),
RK3308_ADC_CH1_MIC_GAIN_SFT,
RK3308_ADC_CH1_MIC_GAIN_MIN,
RK3308_ADC_CH1_MIC_GAIN_MAX,
0, rk3308_codec_adc_mic_gain_tlv),
0, rk3308_codec_adc_3_8_mic_gain_tlv),
SOC_SINGLE_RANGE_TLV("ADC MIC Group 3 Right Volume",
RK3308_ADC_ANA_CON01(3),
RK3308_ADC_CH2_MIC_GAIN_SFT,
RK3308_ADC_CH2_MIC_GAIN_MIN,
RK3308_ADC_CH2_MIC_GAIN_MAX,
0, rk3308_codec_adc_mic_gain_tlv),
0, rk3308_codec_adc_3_8_mic_gain_tlv),
/* ADC ALC */
SOC_SINGLE_RANGE_TLV("ADC ALC Group 0 Left Volume",

22
sound/soc/codecs/rk3308_codec.h
View File

@@ -614,22 +614,30 @@
#define RK3308_ADC_CH1_BUF_REF_EN (0x1 << 0)
#define RK3308_ADC_CH1_BUF_REF_DIS (0x0 << 0)
/* RK3308_ADC_ANA_CON01 - REG: 0x0344 */
/* RK3308_ADC_ANA_CON01 - REG: 0x0344
*
* The PGA of MIC-INs:
* 0x0 - MIC1~MIC8 0dB
* 0x1 - MIC1~MIC2 are invalid, MIC3~MIC8 6.6dB
* 0x2 - MIC1~MIC2 are invalid, MIC3~MIC8 13dB
* 0x3 - MIC1~MIC8 20dB
*/
#define RK3308_ADC_CH2_MIC_GAIN_MAX 0x3
#define RK3308_ADC_CH2_MIC_GAIN_MIN 0
#define RK3308_ADC_CH2_MIC_GAIN_SFT 4
#define RK3308_ADC_CH2_MIC_GAIN_MSK (0x3 << RK3308_ADC_CH2_MIC_GAIN_SFT)
#define RK3308_ADC_CH2_MIC_GAIN_30DB (0x3 << RK3308_ADC_CH2_MIC_GAIN_SFT)
#define RK3308_ADC_CH2_MIC_GAIN_20DB (0x2 << RK3308_ADC_CH2_MIC_GAIN_SFT)
#define RK3308_ADC_CH2_MIC_GAIN_6DB (0x1 << RK3308_ADC_CH2_MIC_GAIN_SFT)
#define RK3308_ADC_CH2_MIC_GAIN_20DB (0x3 << RK3308_ADC_CH2_MIC_GAIN_SFT)
#define RK3308_ADC_3_8_CH2_MIC_GAIN_13DB (0x2 << RK3308_ADC_CH2_MIC_GAIN_SFT)
#define RK3308_ADC_3_8_CH2_MIC_GAIN_6_6DB (0x1 << RK3308_ADC_CH2_MIC_GAIN_SFT)
#define RK3308_ADC_CH2_MIC_GAIN_0DB (0x0 << RK3308_ADC_CH2_MIC_GAIN_SFT)
#define RK3308_ADC_CH1_MIC_GAIN_MAX 0x3
#define RK3308_ADC_CH1_MIC_GAIN_MIN 0
#define RK3308_ADC_CH1_MIC_GAIN_SFT 0
#define RK3308_ADC_CH1_MIC_GAIN_MSK (0x3 << RK3308_ADC_CH1_MIC_GAIN_SFT)
#define RK3308_ADC_CH1_MIC_GAIN_30DB (0x3 << RK3308_ADC_CH1_MIC_GAIN_SFT)
#define RK3308_ADC_CH1_MIC_GAIN_20DB (0x2 << RK3308_ADC_CH1_MIC_GAIN_SFT)
#define RK3308_ADC_CH1_MIC_GAIN_6DB (0x1 << RK3308_ADC_CH1_MIC_GAIN_SFT)
#define RK3308_ADC_CH1_MIC_GAIN_20DB (0x3 << RK3308_ADC_CH1_MIC_GAIN_SFT)
#define RK3308_ADC_3_8_CH1_MIC_GAIN_13DB (0x2 << RK3308_ADC_CH1_MIC_GAIN_SFT)
#define RK3308_ADC_3_8_CH1_MIC_GAIN_6_6DB (0x1 << RK3308_ADC_CH1_MIC_GAIN_SFT)
#define RK3308_ADC_CH1_MIC_GAIN_0DB (0x0 << RK3308_ADC_CH1_MIC_GAIN_SFT)
/* RK3308_ADC_ANA_CON02 - REG: 0x0348 */