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https://github.com/hardkernel/linux.git
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ARM64: dts: rk3368-android: remove rkfb related nodes
Change-Id: I6a180419aabd705736fa1274c3463bad0cb95304 Signed-off-by: Zorro Liu <lyx@rock-chips.com> Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
This commit is contained in:
Zorro Liu
@@ -40,14 +40,7 @@
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/display/rk_fb.h>
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#include <dt-bindings/display/mipi_dsi.h>
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/ {
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aliases {
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lcdc = &lcdc;
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};
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chosen {
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bootargs = "earlycon=uart8250,mmio32,0xff690000 swiotlb=1 firmware_class.path=/system/vendor/firmware";
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};
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@@ -147,76 +140,6 @@
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status = "disabled";
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};
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fb {
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compatible = "rockchip,rk-fb";
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status = "okay";
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rockchip,disp-mode = <NO_DUAL>;
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rockchip,uboot-logo-on = <0>;
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};
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screen {
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compatible = "rockchip,screen";
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status = "okay";
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#include <dt-bindings/display/screen-timing/lcd-tv080wum-mipi.dtsi>
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};
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lcdc: lcdc@ff930000 {
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compatible = "rockchip,rk3368-lcdc";
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rockchip,grf = <&grf>;
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rockchip,pmugrf = <&pmugrf>;
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rockchip,cru = <&cru>;
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rockchip,prop = <PRMRY>;
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rockchip,pwr18 = <0>;
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rockchip,iommu-enabled = <1>;
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reg = <0x0 0xff930000 0x0 0x10000>;
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
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clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
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assigned-clocks = <&cru ACLK_VOP>;
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assigned-clock-rates = <400000000>;
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power-domains = <&power RK3368_PD_VIO>;
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resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
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reset-names = "axi", "ahb", "dclk";
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};
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mipi: mipi@ff960000 {
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compatible = "rockchip,rk3368-dsi";
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rockchip,prop = <0>;
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reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
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reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
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interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
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clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
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power-domains = <&power RK3368_PD_VIO>;
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};
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lvds: lvds@ff968000 {
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compatible = "rockchip,rk3368-lvds";
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rockchip,grf = <&grf>;
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reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
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reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
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clocks = <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
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clock-names = "pclk_lvds", "pclk_lvds_ctl";
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power-domains = <&power RK3368_PD_VIO>;
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status = "disabled";
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};
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edp: edp@ff970000 {
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compatible = "rockchip,rk32-edp";
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reg = <0x0 0xff970000 0x0 0x4000>;
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rockchip,grf = <&grf>;
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interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
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clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
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power-domains = <&power RK3368_PD_VIO>;
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resets = <&cru SRST_EDP_24M>, <&cru SRST_EDP>;
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reset-names = "edp_24m", "edp_apb";
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status = "disabled";
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};
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hdmi: hdmi@ff980000 {
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compatible = "rockchip,rk3368-hdmi";
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reg = <0x0 0xff980000 0x0 0x20000>;
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@@ -234,65 +157,6 @@
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status = "okay";
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};
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iep-mmu {
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dbgname = "iep";
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compatible = "rockchip,iep_mmu";
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reg = <0x0 0xff900800 0x0 0x100>;
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "iep_mmu";
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};
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vip-mmu {
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dbgname = "vip";
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compatible = "rockchip,vip_mmu";
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reg = <0x0 0xff950800 0x0 0x100>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "vip_mmu";
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};
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vopb-mmu {
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dbgname = "vop";
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compatible = "rockchip,vopb_mmu";
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reg = <0x0 0xff930300 0x0 0x100>;
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "vop_mmu";
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};
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isp-mmu {
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dbgname = "isp_mmu";
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compatible = "rockchip,isp_mmu";
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reg = <0x0 0xff914000 0x0 0x100>,
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<0x0 0xff915000 0x0 0x100>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "isp_mmu";
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};
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hdcp-mmu {
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dbgname = "hdcp_mmu";
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compatible = "rockchip,hdcp_mmu";
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reg = <0x0 0xff940000 0x0 0x100>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hdcp_mmu";
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};
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hevc-mmu {
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dbgname = "hevc";
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compatible = "rockchip,hevc_mmu";
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reg = <0x0 0xff9a0440 0x0 0x40>,
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<0x0 0xff9a0480 0x0 0x40>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hevc_mmu";
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};
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vpu-mmu {
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dbgname = "vpu";
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compatible = "rockchip,vpu_mmu";
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reg = <0x0 0xff9a0800 0x0 0x100>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "vepu_mmu", "vdpu_mmu";
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};
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dwc_control_usb: dwc-control-usb {
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compatible = "rockchip,rk3368-dwc-control-usb";
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status = "okay";
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@@ -342,34 +206,6 @@
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rockchip,usb-mode = <0>;
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};
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&lcdc {
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status = "okay";
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backlight = <&backlight>;
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rockchip,mirror = <NO_MIRROR>;
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rockchip,cabc_mode = <0>;
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rockchip,fb-win-map = <FB_DEFAULT_ORDER>;
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power_ctr: power_ctr {
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rockchip,debug = <0>;
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lcd_en: lcd-en {
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rockchip,power_type = <GPIO>;
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gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;/*GPIO_C6 = 22*/
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rockchip,delay = <120>;
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};
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lcd_cs: lcd-cs {
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rockchip,power_type = <GPIO>;
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gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;/*GPIO_C5 = 21*/
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rockchip,delay = <10>;
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};
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/*lcd_rst: lcd-rst {
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rockchip,power_type = <GPIO>;
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gpios = <&gpio3 GPIO_D6 GPIO_ACTIVE_HIGH>;
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rockchip,delay = <5>;
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};*/
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};
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};
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&pinctrl {
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hdmi_i2c {
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hdmii2c_xfer: hdmii2c-xfer {
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@@ -391,52 +227,6 @@
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};
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};
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lcdc {
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lcdc_lcdc: lcdc-lcdc {
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rockchip,pins =
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<0 14 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
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<0 15 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
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<0 16 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
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<0 17 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
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<0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
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<0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
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<0 20 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
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<0 21 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
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<0 22 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
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<0 23 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
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<0 24 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
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<0 25 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
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<0 26 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
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<0 27 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
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<0 31 RK_FUNC_1 &pcfg_pull_none>,//DCLK
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<0 30 RK_FUNC_1 &pcfg_pull_none>,//DEN
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<0 28 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
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<0 29 RK_FUNC_1 &pcfg_pull_none>;//VSYN
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};
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lcdc_gpio: lcdc-gpio {
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rockchip,pins =
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<0 14 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
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<0 15 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
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<0 16 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
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<0 17 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
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<0 18 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
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<0 19 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
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<0 20 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
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<0 21 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
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<0 22 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
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<0 23 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
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<0 24 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
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<0 25 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
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<0 26 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
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<0 27 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
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<0 31 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
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<0 30 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
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<0 28 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
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<0 29 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
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};
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};
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isp {
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cif_clkout: cif-clkout {
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rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
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