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swj add pwm reinit function for reboot

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root
2011-03-04 09:56:25 +08:00
parent 71d7d8f486
commit d1bde7242d
1 changed files with 36 additions and 0 deletions
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36
arch/arm/mach-rk29/reset.c
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@@ -4,6 +4,22 @@
#include <asm/cacheflush.h>
#include <mach/rk29_iomap.h>
#include <mach/cru.h>
#include <linux/clk.h>
#include <linux/mm.h>
#include <linux/sched.h>
#include <linux/mmzone.h>
#include <linux/rtc.h>
#include <asm/tlb.h>
#include <asm/traps.h>
#include <asm/sections.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/stacktrace.h>
#define cru_readl(offset) readl(RK29_CRU_BASE + offset)
#define cru_writel(v, offset) do { writel(v, RK29_CRU_BASE + offset); readl(RK29_CRU_BASE + offset); } while (0)
@@ -15,12 +31,29 @@ static inline void delay_500ns(void)
barrier();
}
static void pwm2gpiodefault(void)
{
#define REG_FILE_BASE_ADDR RK29_GRF_BASE
volatile unsigned int * pGRF_GPIO2L_IOMUX = (volatile unsigned int *)(REG_FILE_BASE_ADDR + 0x58);
#define GPIO2_BASE_ADDR RK29_GPIO2_BASE
volatile unsigned int *pGPIO2_DIR = (volatile unsigned int *)(GPIO2_BASE_ADDR + 0x4);
volatile unsigned int *pGPIO2_LEVEL = (volatile unsigned int *)GPIO2_BASE_ADDR;
// iomux pwm2 to gpio2_a[3]
*pGRF_GPIO2L_IOMUX &= ~(0x3<<6);
// set gpio to input
*pGPIO2_DIR &= ~(0x1<<3);
}
void rk29_arch_reset(int mode, const char *cmd)
{
u32 pll, reg;
local_irq_disable();
local_fiq_disable();
pwm2gpiodefault();
cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CPU_MODE_MASK) | CRU_CPU_MODE_SLOW, CRU_MODE_CON);
@@ -68,6 +101,8 @@ void rk29_arch_reset(int mode, const char *cmd)
"bic r0, %0, #(1 << 0) @disable mmu\n\t"
"bic r0, %0, #(1 << 12) @disable I CACHE\n\t"
"bic r0, %0, #(1 << 2) @disable D DACHE\n\t"
"bic r0, %0, #(1 << 11) @disable \n\t"
"bic r0, %0, #(1 << 28) @disable \n\t"
"mcr p15, 0, %0, c1, c0, 0\n\t"
// "mcr p15, 0, %0, c8, c7, 0 @ invalidate whole TLB\n\t"
// "mcr p15, 0, %0, c7, c5, 6 @ invalidate BTC\n\t"
@@ -81,3 +116,4 @@ void rk29_arch_reset(int mode, const char *cmd)
"mov pc, #0" : : "r" (reg));
}