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clk: rockchip: rk322x: fix up the gate con description error

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Change-Id: I439314c590a7144fab6e33d1fb4f325530669842
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang
2018-12-25 14:58:30 +08:00
parent 557cbe628d
commit d2f238a541
1 changed files with 3 additions and 3 deletions
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6
drivers/clk/rockchip/clk-rk3228.c
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@@ -239,11 +239,11 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
/* PD_CORE */
GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
PX30_CLKGATE_CON(0), 6, GFLAGS),
RK2928_CLKGATE_CON(0), 6, GFLAGS),
GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
PX30_CLKGATE_CON(0), 6, GFLAGS),
RK2928_CLKGATE_CON(0), 6, GFLAGS),
GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED,
PX30_CLKGATE_CON(0), 6, GFLAGS),
RK2928_CLKGATE_CON(0), 6, GFLAGS),
COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED,
RK2928_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK2928_CLKGATE_CON(4), 1, GFLAGS),