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synced 2026-06-03 17:51:57 +09:00
net: sparx5: Add support for ptp interrupts
When doing 2-step timestamping the HW will generate an interrupt when it managed to timestamp a frame. It is the SW responsibility to read it from the FIFO. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
committed by
David S. Miller
parent
70dfe25cd8
commit
d31d37912e
@@ -693,6 +693,18 @@ static int sparx5_start(struct sparx5 *sparx5)
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} else {
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sparx5->xtr_irq = -ENXIO;
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}
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if (sparx5->ptp_irq >= 0) {
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err = devm_request_threaded_irq(sparx5->dev, sparx5->ptp_irq,
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NULL, sparx5_ptp_irq_handler,
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IRQF_ONESHOT, "sparx5-ptp",
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sparx5);
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if (err)
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sparx5->ptp_irq = -ENXIO;
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sparx5->ptp = 1;
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}
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return err;
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}
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@@ -809,6 +821,7 @@ static int mchp_sparx5_probe(struct platform_device *pdev)
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sparx5->fdma_irq = platform_get_irq_byname(sparx5->pdev, "fdma");
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sparx5->xtr_irq = platform_get_irq_byname(sparx5->pdev, "xtr");
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sparx5->ptp_irq = platform_get_irq_byname(sparx5->pdev, "ptp");
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/* Read chip ID to check CPU interface */
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sparx5->chip_id = spx5_rd(sparx5, GCB_CHIP_ID);
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@@ -270,6 +270,7 @@ struct sparx5 {
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spinlock_t ptp_ts_id_lock; /* lock for ts_id */
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struct mutex ptp_lock; /* lock for ptp interface state */
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u16 ptp_skbs;
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int ptp_irq;
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};
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/* sparx5_switchdev.c */
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@@ -355,6 +356,7 @@ int sparx5_ptp_txtstamp_request(struct sparx5_port *port,
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struct sk_buff *skb);
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void sparx5_ptp_txtstamp_release(struct sparx5_port *port,
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struct sk_buff *skb);
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irqreturn_t sparx5_ptp_irq_handler(int irq, void *args);
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/* Clock period in picoseconds */
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static inline u32 sparx5_clk_period(enum sparx5_core_clockfreq cclock)
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@@ -271,6 +271,125 @@ void sparx5_ptp_txtstamp_release(struct sparx5_port *port,
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spin_unlock_irqrestore(&sparx5->ptp_ts_id_lock, flags);
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}
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static void sparx5_get_hwtimestamp(struct sparx5 *sparx5,
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struct timespec64 *ts,
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u32 nsec)
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{
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/* Read current PTP time to get seconds */
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unsigned long flags;
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u32 curr_nsec;
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spin_lock_irqsave(&sparx5->ptp_clock_lock, flags);
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spx5_rmw(PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(PTP_PIN_ACTION_SAVE) |
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PTP_PTP_PIN_CFG_PTP_PIN_DOM_SET(SPARX5_PHC_PORT) |
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PTP_PTP_PIN_CFG_PTP_PIN_SYNC_SET(0),
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PTP_PTP_PIN_CFG_PTP_PIN_ACTION |
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PTP_PTP_PIN_CFG_PTP_PIN_DOM |
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PTP_PTP_PIN_CFG_PTP_PIN_SYNC,
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sparx5, PTP_PTP_PIN_CFG(TOD_ACC_PIN));
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ts->tv_sec = spx5_rd(sparx5, PTP_PTP_TOD_SEC_LSB(TOD_ACC_PIN));
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curr_nsec = spx5_rd(sparx5, PTP_PTP_TOD_NSEC(TOD_ACC_PIN));
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ts->tv_nsec = nsec;
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/* Sec has incremented since the ts was registered */
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if (curr_nsec < nsec)
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ts->tv_sec--;
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spin_unlock_irqrestore(&sparx5->ptp_clock_lock, flags);
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}
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irqreturn_t sparx5_ptp_irq_handler(int irq, void *args)
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{
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int budget = SPARX5_MAX_PTP_ID;
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struct sparx5 *sparx5 = args;
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while (budget--) {
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struct sk_buff *skb, *skb_tmp, *skb_match = NULL;
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struct skb_shared_hwtstamps shhwtstamps;
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struct sparx5_port *port;
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struct timespec64 ts;
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unsigned long flags;
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u32 val, id, txport;
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u32 delay;
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val = spx5_rd(sparx5, REW_PTP_TWOSTEP_CTRL);
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/* Check if a timestamp can be retrieved */
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if (!(val & REW_PTP_TWOSTEP_CTRL_PTP_VLD))
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break;
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WARN_ON(val & REW_PTP_TWOSTEP_CTRL_PTP_OVFL);
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if (!(val & REW_PTP_TWOSTEP_CTRL_STAMP_TX))
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continue;
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/* Retrieve the ts Tx port */
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txport = REW_PTP_TWOSTEP_CTRL_STAMP_PORT_GET(val);
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/* Retrieve its associated skb */
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port = sparx5->ports[txport];
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/* Retrieve the delay */
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delay = spx5_rd(sparx5, REW_PTP_TWOSTEP_STAMP);
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delay = REW_PTP_TWOSTEP_STAMP_STAMP_NSEC_GET(delay);
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/* Get next timestamp from fifo, which needs to be the
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* rx timestamp which represents the id of the frame
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*/
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spx5_rmw(REW_PTP_TWOSTEP_CTRL_PTP_NXT_SET(1),
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REW_PTP_TWOSTEP_CTRL_PTP_NXT,
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sparx5, REW_PTP_TWOSTEP_CTRL);
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val = spx5_rd(sparx5, REW_PTP_TWOSTEP_CTRL);
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/* Check if a timestamp can be retried */
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if (!(val & REW_PTP_TWOSTEP_CTRL_PTP_VLD))
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break;
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/* Read RX timestamping to get the ID */
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id = spx5_rd(sparx5, REW_PTP_TWOSTEP_STAMP);
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id <<= 8;
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id |= spx5_rd(sparx5, REW_PTP_TWOSTEP_STAMP_SUBNS);
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spin_lock_irqsave(&port->tx_skbs.lock, flags);
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skb_queue_walk_safe(&port->tx_skbs, skb, skb_tmp) {
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if (SPARX5_SKB_CB(skb)->ts_id != id)
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continue;
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__skb_unlink(skb, &port->tx_skbs);
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skb_match = skb;
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break;
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}
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spin_unlock_irqrestore(&port->tx_skbs.lock, flags);
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/* Next ts */
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spx5_rmw(REW_PTP_TWOSTEP_CTRL_PTP_NXT_SET(1),
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REW_PTP_TWOSTEP_CTRL_PTP_NXT,
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sparx5, REW_PTP_TWOSTEP_CTRL);
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if (WARN_ON(!skb_match))
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continue;
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spin_lock(&sparx5->ptp_ts_id_lock);
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sparx5->ptp_skbs--;
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spin_unlock(&sparx5->ptp_ts_id_lock);
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/* Get the h/w timestamp */
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sparx5_get_hwtimestamp(sparx5, &ts, delay);
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/* Set the timestamp into the skb */
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shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec);
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skb_tstamp_tx(skb_match, &shhwtstamps);
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dev_kfree_skb_any(skb_match);
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}
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return IRQ_HANDLED;
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}
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static int sparx5_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
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{
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struct sparx5_phc *phc = container_of(ptp, struct sparx5_phc, info);
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