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drm/rockchip: vop2: Add axi id configuration

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Two axi bus:
AXI0 is a read/write bus with a higher performance.
AXI1 is a read only bus.

Every window on a AXI bus must assigned two unique
read id(yrgb_id/uv_id, valid id are 0x1~0xe).

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: I867df219797da33f89fec6fba639bcdf55cb54b3
This commit is contained in:
Andy Yan
2021-11-14 17:32:14 +08:00
committed by Tao Huang
parent 21f2fd663e
commit d43135dfce
4 changed files with 119 additions and 2 deletions
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6
drivers/gpu/drm/rockchip/rockchip_drm_vop.h
View File

@@ -600,6 +600,9 @@ struct vop2_win_regs {
struct vop_reg color_key;
struct vop_reg color_key_en;
struct vop_reg dither_up;
struct vop_reg axi_id;
struct vop_reg axi_yrgb_id;
struct vop_reg axi_uv_id;
};
struct vop2_video_port_regs {
@@ -784,6 +787,9 @@ struct vop2_win_data {
uint8_t phys_id;
uint8_t splice_win_id;
uint8_t pd_id;
uint8_t axi_id;
uint8_t axi_yrgb_id;
uint8_t axi_uv_id;
uint32_t base;
enum drm_plane_type type;

40
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
View File

@@ -370,6 +370,10 @@ struct vop2_win {
uint8_t old_vp_mask;
uint8_t zpos;
uint32_t offset;
uint8_t axi_id;
uint8_t axi_yrgb_id;
uint8_t axi_uv_id;
enum drm_plane_type type;
unsigned int max_upscale_factor;
unsigned int max_downscale_factor;
@@ -1749,11 +1753,21 @@ static bool rockchip_vop2_mod_supported(struct drm_plane *plane, u32 format, u64
return vop2_convert_afbc_format(format) >= 0;
}
static inline bool vop2_multi_area_sub_window(struct vop2_win *win)
{
return (win->parent && (win->feature & WIN_FEATURE_MULTI_AREA));
}
static inline bool vop2_cluster_window(struct vop2_win *win)
{
return (win->feature & (WIN_FEATURE_CLUSTER_MAIN | WIN_FEATURE_CLUSTER_SUB));
}
static inline bool vop2_cluster_sub_window(struct vop2_win *win)
{
return (win->feature & WIN_FEATURE_CLUSTER_SUB);
}
static inline bool vop2_has_feature(struct vop2 *vop2, uint64_t feature)
{
return (vop2->data->feature & feature);
@@ -3583,6 +3597,26 @@ static void vop2_calc_drm_rect_for_splice(struct vop2_plane_state *vpstate,
right_dst->y2 = dst->y2;
}
static void rk3588_vop2_win_cfg_axi(struct vop2_win *win)
{
struct vop2 *vop2 = win->vop2;
/*
* No need to set multi area sub windows as it
* share the same axi bus and read_id with main window.
*/
if (vop2_multi_area_sub_window(win))
return;
/*
* No need to set Cluster sub windows axi_id as it
* share the same axi bus with main window.
*/
if (!vop2_cluster_sub_window(win))
VOP_WIN_SET(vop2, win, axi_id, win->axi_id);
VOP_WIN_SET(vop2, win, axi_yrgb_id, win->axi_yrgb_id);
VOP_WIN_SET(vop2, win, axi_uv_id, win->axi_uv_id);
}
static void vop2_win_atomic_update(struct vop2_win *win, struct drm_rect *src, struct drm_rect *dst,
struct drm_plane_state *pstate)
{
@@ -3702,6 +3736,9 @@ static void vop2_win_atomic_update(struct vop2_win *win, struct drm_rect *src, s
drm_get_format_name(fb->format->format, &format_name),
vpstate->afbc_en ? "AFBC" : "", &vpstate->yrgb_mst);
if (vop2->version != VOP_VERSION_RK3568)
rk3588_vop2_win_cfg_axi(win);
if (vpstate->afbc_en) {
/* the afbc superblock is 16 x 16 */
afbc_format = vop2_convert_afbc_format(fb->format->format);
@@ -7824,6 +7861,9 @@ static int vop2_win_init(struct vop2 *vop2)
win->area_id = 0;
win->zpos = i;
win->vop2 = vop2;
win->axi_id = win_data->axi_id;
win->axi_yrgb_id = win_data->axi_yrgb_id;
win->axi_uv_id = win_data->axi_uv_id;
if (win_data->pd_id)
win->pd = vop2_find_pd_by_id(vop2, win_data->pd_id);

70
drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
View File

@@ -1638,6 +1638,9 @@ static const struct vop2_win_regs rk3568_cluster0_win_data = {
.y2r_en = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 8),
.r2y_en = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 9),
.csc_mode = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x3, 10),
.axi_yrgb_id = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL2, 0x1f, 0),
.axi_uv_id = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL2, 0x1f, 5),
.axi_id = VOP_REG(RK3568_CLUSTER0_CTRL, 0x1, 13),
};
static const struct vop2_win_regs rk3568_cluster1_win_data = {
@@ -1658,6 +1661,9 @@ static const struct vop2_win_regs rk3568_cluster1_win_data = {
.y2r_en = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL0, 0x1, 8),
.r2y_en = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL0, 0x1, 9),
.csc_mode = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL0, 0x3, 10),
.axi_yrgb_id = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL2, 0x1f, 0),
.axi_uv_id = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL2, 0x1f, 5),
.axi_id = VOP_REG(RK3568_CLUSTER1_CTRL, 0x1, 13),
};
static const struct vop2_win_regs rk3588_cluster2_win_data = {
@@ -1677,6 +1683,9 @@ static const struct vop2_win_regs rk3588_cluster2_win_data = {
.y2r_en = VOP_REG(RK3588_CLUSTER2_WIN0_CTRL0, 0x1, 8),
.r2y_en = VOP_REG(RK3588_CLUSTER2_WIN0_CTRL0, 0x1, 9),
.csc_mode = VOP_REG(RK3588_CLUSTER2_WIN0_CTRL0, 0x3, 10),
.axi_yrgb_id = VOP_REG(RK3588_CLUSTER2_WIN0_CTRL2, 0x1f, 0),
.axi_uv_id = VOP_REG(RK3588_CLUSTER2_WIN0_CTRL2, 0x1f, 5),
.axi_id = VOP_REG(RK3588_CLUSTER2_CTRL, 0x1, 13),
};
static const struct vop2_win_regs rk3588_cluster3_win_data = {
@@ -1696,10 +1705,16 @@ static const struct vop2_win_regs rk3588_cluster3_win_data = {
.y2r_en = VOP_REG(RK3588_CLUSTER3_WIN0_CTRL0, 0x1, 8),
.r2y_en = VOP_REG(RK3588_CLUSTER3_WIN0_CTRL0, 0x1, 9),
.csc_mode = VOP_REG(RK3588_CLUSTER3_WIN0_CTRL0, 0x3, 10),
.axi_yrgb_id = VOP_REG(RK3588_CLUSTER3_WIN0_CTRL2, 0x1f, 0),
.axi_uv_id = VOP_REG(RK3588_CLUSTER3_WIN0_CTRL2, 0x1f, 5),
.axi_id = VOP_REG(RK3588_CLUSTER3_CTRL, 0x1, 13),
};
static const struct vop2_win_regs rk3568_esmart_win_data = {
.scl = &rk3568_esmart_win_scl,
.axi_yrgb_id = VOP_REG(RK3568_ESMART0_CTRL1, 0x1f, 4),
.axi_uv_id = VOP_REG(RK3568_ESMART0_CTRL1, 0x1f, 12),
.axi_id = VOP_REG(RK3568_ESMART0_AXI_CTRL, 0x1, 1),
.enable = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 0),
.format = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1f, 1),
.dither_up = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 12),
@@ -2105,6 +2120,19 @@ static const struct vop2_power_domain_data rk3588_vop_mem_pg_data[] = {
* * nearest-neighbor/bilinear/bicubic for scale up
* * nearest-neighbor/bilinear/average for scale down
*
* AXI Read ID assignment:
* Two AXI bus:
* AXI0 is a read/write bus with a higher performance.
* AXI1 is a read only bus.
*
* Every window on a AXI bus must assigned two unique
* read id(yrgb_id/uv_id, valid id are 0x1~0xe).
*
* AXI0:
* Cluster0/1, Esmart0/1, WriteBack
*
* AXI 1:
* Cluster2/3, Esmart2/3
*
* @TODO describe the wind like cpu-map dt nodes;
*/
@@ -2126,6 +2154,9 @@ static const struct vop2_win_data rk3588_vop_win_data[] = {
.vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
.regs = &rk3568_cluster0_win_data,
.pd_id = VOP2_PD_CLUSTER0,
.axi_id = 0,
.axi_yrgb_id = 2,
.axi_uv_id = 3,
.max_upscale_factor = 4,
.max_downscale_factor = 4,
.dly = { 4, 26, 29 },
@@ -2147,6 +2178,9 @@ static const struct vop2_win_data rk3588_vop_win_data[] = {
.vsu_filter_mode = VOP2_SCALE_UP_BIL,
.vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
.regs = &rk3568_cluster0_win_data,
.axi_id = 0,
.axi_yrgb_id = 4,
.axi_uv_id = 5,
.max_upscale_factor = 4,
.max_downscale_factor = 4,
.type = DRM_PLANE_TYPE_OVERLAY,
@@ -2169,6 +2203,9 @@ static const struct vop2_win_data rk3588_vop_win_data[] = {
.vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
.regs = &rk3568_cluster1_win_data,
.pd_id = VOP2_PD_CLUSTER1,
.axi_id = 0,
.axi_yrgb_id = 6,
.axi_uv_id = 7,
.type = DRM_PLANE_TYPE_OVERLAY,
.max_upscale_factor = 4,
.max_downscale_factor = 4,
@@ -2191,6 +2228,9 @@ static const struct vop2_win_data rk3588_vop_win_data[] = {
.vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
.regs = &rk3568_cluster1_win_data,
.type = DRM_PLANE_TYPE_OVERLAY,
.axi_id = 0,
.axi_yrgb_id = 8,
.axi_uv_id = 9,
.max_upscale_factor = 4,
.max_downscale_factor = 4,
.feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_SUB,
@@ -2214,6 +2254,9 @@ static const struct vop2_win_data rk3588_vop_win_data[] = {
.vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
.regs = &rk3588_cluster2_win_data,
.type = DRM_PLANE_TYPE_OVERLAY,
.axi_id = 1,
.axi_yrgb_id = 2,
.axi_uv_id = 3,
.max_upscale_factor = 4,
.max_downscale_factor = 4,
.dly = { 4, 26, 29 },
@@ -2235,6 +2278,9 @@ static const struct vop2_win_data rk3588_vop_win_data[] = {
.vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
.regs = &rk3588_cluster2_win_data,
.type = DRM_PLANE_TYPE_OVERLAY,
.axi_id = 1,
.axi_yrgb_id = 4,
.axi_uv_id = 5,
.max_upscale_factor = 4,
.max_downscale_factor = 4,
.feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_SUB,
@@ -2257,6 +2303,9 @@ static const struct vop2_win_data rk3588_vop_win_data[] = {
.vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
.regs = &rk3588_cluster3_win_data,
.type = DRM_PLANE_TYPE_OVERLAY,
.axi_id = 1,
.axi_yrgb_id = 6,
.axi_uv_id = 7,
.max_upscale_factor = 4,
.max_downscale_factor = 4,
.dly = { 4, 26, 29 },
@@ -2278,6 +2327,9 @@ static const struct vop2_win_data rk3588_vop_win_data[] = {
.vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
.regs = &rk3588_cluster3_win_data,
.type = DRM_PLANE_TYPE_OVERLAY,
.axi_id = 1,
.axi_yrgb_id = 8,
.axi_uv_id = 9,
.max_upscale_factor = 4,
.max_downscale_factor = 4,
.feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_SUB,
@@ -2302,10 +2354,13 @@ static const struct vop2_win_data rk3588_vop_win_data[] = {
.area = rk3568_area_data,
.area_size = ARRAY_SIZE(rk3568_area_data),
.type = DRM_PLANE_TYPE_PRIMARY,
.axi_id = 0,
.axi_yrgb_id = 0x0a,
.axi_uv_id = 0x0b,
.max_upscale_factor = 8,
.max_downscale_factor = 8,
.dly = { 23, 45, 48 },
.feature = WIN_FEATURE_SPLICE_LEFT,
.feature = WIN_FEATURE_SPLICE_LEFT | WIN_FEATURE_MULTI_AREA,
},
{
@@ -2327,10 +2382,13 @@ static const struct vop2_win_data rk3588_vop_win_data[] = {
.area = rk3568_area_data,
.area_size = ARRAY_SIZE(rk3568_area_data),
.type = DRM_PLANE_TYPE_PRIMARY,
.axi_id = 1,
.axi_yrgb_id = 0x0a,
.axi_uv_id = 0x0b,
.max_upscale_factor = 8,
.max_downscale_factor = 8,
.dly = { 23, 45, 48 },
.feature = WIN_FEATURE_SPLICE_LEFT,
.feature = WIN_FEATURE_SPLICE_LEFT | WIN_FEATURE_MULTI_AREA,
},
{
@@ -2351,9 +2409,13 @@ static const struct vop2_win_data rk3588_vop_win_data[] = {
.area = rk3568_area_data,
.area_size = ARRAY_SIZE(rk3568_area_data),
.type = DRM_PLANE_TYPE_PRIMARY,
.axi_id = 0,
.axi_yrgb_id = 0x01,
.axi_uv_id = 0x0d,
.max_upscale_factor = 8,
.max_downscale_factor = 8,
.dly = { 23, 45, 48 },
.feature = WIN_FEATURE_MULTI_AREA,
},
{
@@ -2374,9 +2436,13 @@ static const struct vop2_win_data rk3588_vop_win_data[] = {
.area = rk3568_area_data,
.area_size = ARRAY_SIZE(rk3568_area_data),
.type = DRM_PLANE_TYPE_PRIMARY,
.axi_id = 1,
.axi_yrgb_id = 0x0c,
.axi_uv_id = 0x0d,
.max_upscale_factor = 8,
.max_downscale_factor = 8,
.dly = { 23, 45, 48 },
.feature = WIN_FEATURE_MULTI_AREA,
},
};

5
drivers/gpu/drm/rockchip/rockchip_vop_reg.h
View File

@@ -1234,6 +1234,7 @@
/* Cluster0 register definition */
#define RK3568_CLUSTER0_WIN0_CTRL0 0x1000
#define RK3568_CLUSTER0_WIN0_CTRL1 0x1004
#define RK3568_CLUSTER0_WIN0_CTRL2 0x1008
#define RK3568_CLUSTER0_WIN0_YRGB_MST 0x1010
#define RK3568_CLUSTER0_WIN0_CBR_MST 0x1014
#define RK3568_CLUSTER0_WIN0_VIR 0x1018
@@ -1273,6 +1274,7 @@
#define RK3568_CLUSTER1_WIN0_CTRL0 0x1200
#define RK3568_CLUSTER1_WIN0_CTRL1 0x1204
#define RK3568_CLUSTER1_WIN0_CTRL2 0x1208
#define RK3568_CLUSTER1_WIN0_YRGB_MST 0x1210
#define RK3568_CLUSTER1_WIN0_CBR_MST 0x1214
#define RK3568_CLUSTER1_WIN0_VIR 0x1218
@@ -1312,6 +1314,7 @@
#define RK3588_CLUSTER2_WIN0_CTRL0 0x1400
#define RK3588_CLUSTER2_WIN0_CTRL1 0x1404
#define RK3588_CLUSTER2_WIN0_CTRL2 0x1408
#define RK3588_CLUSTER2_WIN0_YRGB_MST 0x1410
#define RK3588_CLUSTER2_WIN0_CBR_MST 0x1414
#define RK3588_CLUSTER2_WIN0_VIR 0x1418
@@ -1351,6 +1354,7 @@
#define RK3588_CLUSTER3_WIN0_CTRL0 0x1600
#define RK3588_CLUSTER3_WIN0_CTRL1 0x1604
#define RK3588_CLUSTER3_WIN0_CTRL2 0x1608
#define RK3588_CLUSTER3_WIN0_YRGB_MST 0x1610
#define RK3588_CLUSTER3_WIN0_CBR_MST 0x1614
#define RK3588_CLUSTER3_WIN0_VIR 0x1618
@@ -1391,6 +1395,7 @@
/* Esmart register definition */
#define RK3568_ESMART0_CTRL0 0x1800
#define RK3568_ESMART0_CTRL1 0x1804
#define RK3568_ESMART0_AXI_CTRL 0x1808
#define RK3568_ESMART0_REGION0_CTRL 0x1810
#define RK3568_ESMART0_REGION0_YRGB_MST 0x1814
#define RK3568_ESMART0_REGION0_CBR_MST 0x1818