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phy: rockchip: inno-hdmi: Support automatic calculation of the phy pll frequency division coefficient
If the required frequency is not in the pre_pll_cfg_table, the automatically calculated frequency division coefficient will be used. The automatic calculation function has been tested at following frequencies(unit is Mhz): 594/371.25/297/185.625/148.5/108/92.8125/74.25/59.4/33.75/27/25.2 Change-Id: If58e12c284dc315c82043600edec6cb313423550 Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
This commit is contained in:
Algea Cao
@@ -476,6 +476,243 @@ static irqreturn_t inno_hdmi_phy_irq(int irq, void *dev_id)
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return IRQ_HANDLED;
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}
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#define FREF 24000000
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#define FFBD_FRAC_MAX 16777216
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static int inno_hdmi_phy_pll_cal(struct inno_hdmi_phy *inno, struct pre_pll_config *cfg,
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u64 pixelclk, u64 tmdsclock)
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{
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u32 j, k, i, nf = 0, nr = 1, tmds_no, tmds_a, tmds_b, tmds_c;
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u32 pclk_no = 0, prepclk_no = 0, div_5 = 0;
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u8 tmdsa[4] = {1, 2, 3, 5};
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u8 tmdsbc[4] = {1, 2, 4, 8};
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u8 pclkb[4] = {2, 3, 4, 5};
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u8 pclkc[4] = {1, 2, 4, 8};
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u32 pclka, pclkd;
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u32 rem = 0;
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u64 frac_div = 0;
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u64 fvco;
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u64 frefdiv;
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bool frac_supported = true;
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bool frac_cal = false;
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dev_dbg(inno->dev, "pixelclk:%llu,tmdsclock:%llu\n", pixelclk, tmdsclock);
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if (pixelclk > tmdsclock && pixelclk < 340000000) {
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dev_dbg(inno->dev, "hdmi1.4 resolution can't support yuv420 mode\n");
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return 0;
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}
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if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228)
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frac_supported = false;
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/* VCO frequency shall not be higher than 3.2Ghz */
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i = DIV_ROUND_UP_ULL(3200000000ULL, tmdsclock * 4);
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continue_cal:
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/*
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* If the current parameters can not get the correct clock,
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* return here and continue to calculate with next set of
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* parameters until the allowed range is exceeded or get
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* the correct clock.
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*/
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for (; nr < 31; nr++) {
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frefdiv = FREF / nr;
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nf = 0;
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/* VCO frequency shall not be lower than 1.4Ghz */
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while (((tmdsclock * 4 * --i) > 1400000000ULL) && i > 0) {
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fvco = tmdsclock * 4 * i;
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div_5 = 0;
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div_u64_rem(fvco, frefdiv, &rem);
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dev_dbg(inno->dev, "i:%u rem:%u frefdiv:%llu fvco:%llu\n",
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i, rem, frefdiv, fvco);
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/* fvco = (fref / nr) * nf */
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if (!frac_cal && !rem && (div_u64(fvco, frefdiv) <= 4096)) {
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nf = div_u64(fvco, frefdiv);
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tmds_no = i;
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break;
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/* fvco = (fref / nr) * (nf + frac_div / 2^24) */
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} else if (frac_cal && (div_u64(fvco, frefdiv) <= 4096)) {
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nf = div_u64(fvco, frefdiv);
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tmds_no = i;
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frac_div = (u64)rem * FFBD_FRAC_MAX;
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frac_div = div_u64(frac_div, frefdiv);
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dev_dbg(inno->dev, "frac_div:%llu\n", frac_div);
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break;
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}
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}
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if (nf)
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break;
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i = DIV_ROUND_UP_ULL(3200000000ULL, tmdsclock * 4);
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}
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if (nr == 31) {
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if (frac_supported) {
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/*
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* RK3528/RK3328 support fraction calculation. If this clk can't
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* be calculated with integers, using fraction to
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* calculate.
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*/
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if (!frac_cal) {
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frac_cal = 1;
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nr = 1;
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goto continue_cal;
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}
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}
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dev_dbg(inno->dev, "can't support tmdsclock:%llu\n", tmdsclock);
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return 0;
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}
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if (tmdsclock > 340000000) {
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for (k = 0; k < 4; k++) {
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/*
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* HDMI2.0 is 1/40 mode, tmds lane clk is 1/4 pixel clk.
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* so f_linkclk must be four times that of f_tmdsclk,
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* tmds_divb must be four times that of tmds_divc.
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* The cycle starts from tmdsbc[2].
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*/
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for (j = 2; j < 4; j++) {
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if (tmdsa[k] * tmdsbc[j] == (4 * tmds_no))
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break;
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}
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if (j < 4)
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break;
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}
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} else {
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for (k = 0; k < 4; k++) {
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for (j = 0; j < 4; j++) {
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if (tmdsa[k] * tmdsbc[j] == tmds_no)
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break;
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}
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if (j < 4)
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break;
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}
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}
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if (k == 4) {
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nf = 0;
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goto continue_cal;
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}
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tmds_a = k;
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tmds_b = j;
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if (tmdsclock > 340000000)
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tmds_c = j - 2;
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else
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tmds_c = j;
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dev_dbg(inno->dev, "tmds_a %d (%d) tmds_b %d (%d) tmds_c %d (%d)\n",
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tmds_a, tmdsa[tmds_a], tmds_b, tmdsbc[tmds_b], tmds_c,
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tmdsbc[tmds_c]);
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/* In yuv420 mode f_pclk is twice of f_prepclk */
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if (pixelclk > tmdsclock) {
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div_u64_rem(fvco * 2, pixelclk, &rem);
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if (rem)
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goto continue_cal;
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prepclk_no = div_u64(fvco * 2, pixelclk);
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if (div_u64(fvco, pixelclk) == 5) {
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div_5 = 1;
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} else {
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if (prepclk_no % 4)
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goto continue_cal;
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pclk_no = prepclk_no / 4;
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}
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} else {
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div_u64_rem(fvco, pixelclk, &rem);
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if (rem)
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goto continue_cal;
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prepclk_no = div_u64(fvco, pixelclk);
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if (div_u64(fvco, pixelclk) == 5) {
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div_5 = 1;
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} else {
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if (prepclk_no % 2)
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goto continue_cal;
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pclk_no = prepclk_no / 2;
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}
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}
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dev_dbg(inno->dev, "prepclk_no:%d,pclk_no:%d,div_5:%d\n",
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prepclk_no, pclk_no, div_5);
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for (k = 0; k < 4; k++) {
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for (j = 0; j < 4; j++) {
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if (pclkb[k] * pclkc[j] == prepclk_no)
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break;
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}
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if (j < 4) {
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pclka = 1;
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break;
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}
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}
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if (k == 4) {
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for (j = 0; j < 4; j++) {
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if ((prepclk_no % pclkc[j]) == 0 &&
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(prepclk_no / pclkc[j]) < 32) {
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pclka = prepclk_no / pclkc[j];
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break;
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}
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}
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} else {
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pclka = 1;
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}
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if (j == 4)
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goto continue_cal;
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/* pixel clk directly divided by 5 from fvco */
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if (div_5) {
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pclkd = 1;
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} else {
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if (k == 4) {
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if (pclk_no % pclka)
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goto continue_cal;
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else
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pclkd = pclk_no / pclka;
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} else {
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if (pclk_no % pclkb[k])
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goto continue_cal;
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else
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pclkd = pclk_no / pclkb[k];
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}
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}
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if (cfg) {
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cfg->pixclock = pixelclk;
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cfg->tmdsclock = tmdsclock;
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cfg->prediv = nr;
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cfg->fbdiv = nf;
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cfg->tmds_div_a = tmds_a;
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cfg->tmds_div_b = tmds_b;
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cfg->tmds_div_c = tmds_c;
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cfg->pclk_div_a = pclka;
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cfg->pclk_div_b = k;
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cfg->pclk_div_c = j;
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cfg->pclk_div_d = pclkd;
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cfg->vco_div_5_en = div_5;
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cfg->fracdiv = frac_div;
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}
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dev_dbg(inno->dev, "%llu, %llu, %u, %u, %u, %u, %u, %u, %u, %u, %u, %u, %llu\n",
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pixelclk, tmdsclock, nr, nf, tmds_a, tmds_b, tmds_c, pclka, k, j, pclkd,
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div_5, frac_div);
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return pixelclk;
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}
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static int inno_hdmi_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate);
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@@ -595,36 +832,25 @@ static unsigned long inno_hdmi_phy_clk_recalc_rate(struct clk_hw *hw,
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static long inno_hdmi_phy_clk_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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int i;
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const struct pre_pll_config *cfg = pre_pll_cfg_table;
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struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
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u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate);
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/* Limit pixel clock under 600MHz */
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if (rate > 600000000)
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return -EINVAL;
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for (; cfg->pixclock != ~0UL; cfg++)
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if (cfg->pixclock == rate)
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break;
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/* XXX: Limit pixel clock under 600MHz */
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if (cfg->pixclock > 600000000)
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return -EINVAL;
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if (cfg->pixclock == ~0UL) {
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if (!inno_hdmi_phy_pll_cal(inno, NULL, rate, tmdsclock))
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return -EINVAL;
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/*
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* If there is no dts phy cfg table, use default phy cfg table.
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* The tmds clock maximum is 594MHz. So there is no need to check
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* whether tmds clock is out of range.
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*/
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if (!inno->phy_cfg)
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return cfg->pixclock;
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/* Check if tmds clock is out of dts phy config's range. */
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for (i = 0; inno->phy_cfg[i].tmdsclock != ~0UL; i++) {
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if (inno->phy_cfg[i].tmdsclock >= tmdsclock)
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break;
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return rate;
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}
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if (inno->phy_cfg[i].tmdsclock == ~0UL)
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return -EINVAL;
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return cfg->pixclock;
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}
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@@ -633,6 +859,7 @@ static int inno_hdmi_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate,
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{
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struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
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const struct pre_pll_config *cfg = pre_pll_cfg_table;
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struct pre_pll_config rc = {0};
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u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate);
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dev_dbg(inno->dev, "%s rate %lu tmdsclk %u\n",
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@@ -645,13 +872,17 @@ static int inno_hdmi_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate,
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if (cfg->pixclock == rate && cfg->tmdsclock == tmdsclock)
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break;
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rc = *cfg;
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if (cfg->pixclock == ~0UL) {
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dev_err(inno->dev, "unsupported rate %lu\n", rate);
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return -EINVAL;
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if (!inno_hdmi_phy_pll_cal(inno, &rc, rate, tmdsclock)) {
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dev_err(inno->dev, "unsupported rate %lu\n", rate);
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return -EINVAL;
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}
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}
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if (inno->plat_data->ops->pre_pll_update)
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inno->plat_data->ops->pre_pll_update(inno, cfg);
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inno->plat_data->ops->pre_pll_update(inno, &rc);
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inno->pixclock = rate;
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inno->tmdsclock = tmdsclock;
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