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drm/i915: move pipe update code into crtc. (v2)
Daniel suggested this should move here. v2: move vrr code. Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/738c7aaeb63c7d2357ddd932f18787ec8a3cefeb.1612536383.git.jani.nikula@intel.com
This commit is contained in:
Dave Airlie
@@ -10,6 +10,9 @@
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#include <drm/drm_plane.h>
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#include <drm/drm_plane_helper.h>
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#include "i915_trace.h"
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#include "i915_vgpu.h"
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#include "intel_atomic.h"
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#include "intel_atomic_plane.h"
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#include "intel_color.h"
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@@ -17,8 +20,11 @@
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#include "intel_cursor.h"
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#include "intel_display_debugfs.h"
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#include "intel_display_types.h"
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#include "intel_dsi.h"
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#include "intel_pipe_crc.h"
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#include "intel_psr.h"
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#include "intel_sprite.h"
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#include "intel_vrr.h"
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#include "i9xx_plane.h"
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#include "skl_universal_plane.h"
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@@ -332,3 +338,238 @@ fail:
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return ret;
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}
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int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
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int usecs)
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{
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/* paranoia */
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if (!adjusted_mode->crtc_htotal)
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return 1;
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return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
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1000 * adjusted_mode->crtc_htotal);
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}
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static int intel_mode_vblank_start(const struct drm_display_mode *mode)
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{
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int vblank_start = mode->crtc_vblank_start;
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if (mode->flags & DRM_MODE_FLAG_INTERLACE)
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vblank_start = DIV_ROUND_UP(vblank_start, 2);
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return vblank_start;
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}
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/**
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* intel_pipe_update_start() - start update of a set of display registers
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* @new_crtc_state: the new crtc state
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*
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* Mark the start of an update to pipe registers that should be updated
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* atomically regarding vblank. If the next vblank will happens within
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* the next 100 us, this function waits until the vblank passes.
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*
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* After a successful call to this function, interrupts will be disabled
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* until a subsequent call to intel_pipe_update_end(). That is done to
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* avoid random delays.
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*/
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void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
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{
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struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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const struct drm_display_mode *adjusted_mode = &new_crtc_state->hw.adjusted_mode;
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long timeout = msecs_to_jiffies_timeout(1);
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int scanline, min, max, vblank_start;
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wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
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bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
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intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI);
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DEFINE_WAIT(wait);
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if (new_crtc_state->uapi.async_flip)
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return;
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if (new_crtc_state->vrr.enable)
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vblank_start = intel_vrr_vmax_vblank_start(new_crtc_state);
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else
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vblank_start = intel_mode_vblank_start(adjusted_mode);
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/* FIXME needs to be calibrated sensibly */
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min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
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VBLANK_EVASION_TIME_US);
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max = vblank_start - 1;
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if (min <= 0 || max <= 0)
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goto irq_disable;
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if (drm_WARN_ON(&dev_priv->drm, drm_crtc_vblank_get(&crtc->base)))
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goto irq_disable;
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/*
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* Wait for psr to idle out after enabling the VBL interrupts
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* VBL interrupts will start the PSR exit and prevent a PSR
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* re-entry as well.
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*/
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intel_psr_wait_for_idle(new_crtc_state);
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local_irq_disable();
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crtc->debug.min_vbl = min;
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crtc->debug.max_vbl = max;
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trace_intel_pipe_update_start(crtc);
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for (;;) {
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/*
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* prepare_to_wait() has a memory barrier, which guarantees
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* other CPUs can see the task state update by the time we
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* read the scanline.
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*/
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prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
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scanline = intel_get_crtc_scanline(crtc);
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if (scanline < min || scanline > max)
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break;
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if (!timeout) {
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drm_err(&dev_priv->drm,
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"Potential atomic update failure on pipe %c\n",
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pipe_name(crtc->pipe));
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break;
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}
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local_irq_enable();
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timeout = schedule_timeout(timeout);
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local_irq_disable();
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}
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finish_wait(wq, &wait);
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drm_crtc_vblank_put(&crtc->base);
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/*
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* On VLV/CHV DSI the scanline counter would appear to
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* increment approx. 1/3 of a scanline before start of vblank.
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* The registers still get latched at start of vblank however.
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* This means we must not write any registers on the first
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* line of vblank (since not the whole line is actually in
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* vblank). And unfortunately we can't use the interrupt to
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* wait here since it will fire too soon. We could use the
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* frame start interrupt instead since it will fire after the
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* critical scanline, but that would require more changes
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* in the interrupt code. So for now we'll just do the nasty
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* thing and poll for the bad scanline to pass us by.
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*
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* FIXME figure out if BXT+ DSI suffers from this as well
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*/
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while (need_vlv_dsi_wa && scanline == vblank_start)
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scanline = intel_get_crtc_scanline(crtc);
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crtc->debug.scanline_start = scanline;
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crtc->debug.start_vbl_time = ktime_get();
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crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc);
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trace_intel_pipe_update_vblank_evaded(crtc);
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return;
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irq_disable:
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local_irq_disable();
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}
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#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_VBLANK_EVADE)
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static void dbg_vblank_evade(struct intel_crtc *crtc, ktime_t end)
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{
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u64 delta = ktime_to_ns(ktime_sub(end, crtc->debug.start_vbl_time));
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unsigned int h;
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h = ilog2(delta >> 9);
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if (h >= ARRAY_SIZE(crtc->debug.vbl.times))
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h = ARRAY_SIZE(crtc->debug.vbl.times) - 1;
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crtc->debug.vbl.times[h]++;
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crtc->debug.vbl.sum += delta;
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if (!crtc->debug.vbl.min || delta < crtc->debug.vbl.min)
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crtc->debug.vbl.min = delta;
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if (delta > crtc->debug.vbl.max)
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crtc->debug.vbl.max = delta;
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if (delta > 1000 * VBLANK_EVASION_TIME_US) {
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drm_dbg_kms(crtc->base.dev,
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"Atomic update on pipe (%c) took %lld us, max time under evasion is %u us\n",
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pipe_name(crtc->pipe),
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div_u64(delta, 1000),
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VBLANK_EVASION_TIME_US);
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crtc->debug.vbl.over++;
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}
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}
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#else
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static void dbg_vblank_evade(struct intel_crtc *crtc, ktime_t end) {}
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#endif
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/**
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* intel_pipe_update_end() - end update of a set of display registers
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* @new_crtc_state: the new crtc state
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*
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* Mark the end of an update started with intel_pipe_update_start(). This
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* re-enables interrupts and verifies the update was actually completed
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* before a vblank.
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*/
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void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
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{
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struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
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enum pipe pipe = crtc->pipe;
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int scanline_end = intel_get_crtc_scanline(crtc);
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u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
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ktime_t end_vbl_time = ktime_get();
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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if (new_crtc_state->uapi.async_flip)
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return;
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trace_intel_pipe_update_end(crtc, end_vbl_count, scanline_end);
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/*
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* Incase of mipi dsi command mode, we need to set frame update
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* request for every commit.
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*/
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if (INTEL_GEN(dev_priv) >= 11 &&
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intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
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icl_dsi_frame_update(new_crtc_state);
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/* We're still in the vblank-evade critical section, this can't race.
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* Would be slightly nice to just grab the vblank count and arm the
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* event outside of the critical section - the spinlock might spin for a
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* while ... */
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if (new_crtc_state->uapi.event) {
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drm_WARN_ON(&dev_priv->drm,
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drm_crtc_vblank_get(&crtc->base) != 0);
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spin_lock(&crtc->base.dev->event_lock);
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drm_crtc_arm_vblank_event(&crtc->base,
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new_crtc_state->uapi.event);
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spin_unlock(&crtc->base.dev->event_lock);
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new_crtc_state->uapi.event = NULL;
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}
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local_irq_enable();
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/* Send VRR Push to terminate Vblank */
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intel_vrr_send_push(new_crtc_state);
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if (intel_vgpu_active(dev_priv))
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return;
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if (crtc->debug.start_vbl_count &&
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crtc->debug.start_vbl_count != end_vbl_count) {
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drm_err(&dev_priv->drm,
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"Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
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pipe_name(pipe), crtc->debug.start_vbl_count,
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end_vbl_count,
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ktime_us_delta(end_vbl_time,
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crtc->debug.start_vbl_time),
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crtc->debug.min_vbl, crtc->debug.max_vbl,
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crtc->debug.scanline_start, scanline_end);
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}
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dbg_vblank_evade(crtc, end_vbl_time);
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}
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@@ -45,248 +45,10 @@
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#include "intel_atomic_plane.h"
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#include "intel_display_types.h"
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#include "intel_frontbuffer.h"
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#include "intel_pm.h"
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#include "intel_psr.h"
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#include "intel_dsi.h"
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#include "intel_sprite.h"
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#include "i9xx_plane.h"
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#include "intel_vrr.h"
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int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
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int usecs)
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{
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/* paranoia */
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if (!adjusted_mode->crtc_htotal)
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return 1;
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return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
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1000 * adjusted_mode->crtc_htotal);
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}
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static int intel_mode_vblank_start(const struct drm_display_mode *mode)
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{
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int vblank_start = mode->crtc_vblank_start;
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if (mode->flags & DRM_MODE_FLAG_INTERLACE)
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vblank_start = DIV_ROUND_UP(vblank_start, 2);
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return vblank_start;
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}
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/**
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* intel_pipe_update_start() - start update of a set of display registers
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* @new_crtc_state: the new crtc state
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*
|
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* Mark the start of an update to pipe registers that should be updated
|
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* atomically regarding vblank. If the next vblank will happens within
|
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* the next 100 us, this function waits until the vblank passes.
|
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*
|
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* After a successful call to this function, interrupts will be disabled
|
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* until a subsequent call to intel_pipe_update_end(). That is done to
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* avoid random delays.
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*/
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void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
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{
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struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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const struct drm_display_mode *adjusted_mode = &new_crtc_state->hw.adjusted_mode;
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long timeout = msecs_to_jiffies_timeout(1);
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int scanline, min, max, vblank_start;
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wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
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bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
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intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI);
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DEFINE_WAIT(wait);
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if (new_crtc_state->uapi.async_flip)
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return;
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if (new_crtc_state->vrr.enable)
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vblank_start = intel_vrr_vmax_vblank_start(new_crtc_state);
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else
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vblank_start = intel_mode_vblank_start(adjusted_mode);
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/* FIXME needs to be calibrated sensibly */
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min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
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VBLANK_EVASION_TIME_US);
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max = vblank_start - 1;
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if (min <= 0 || max <= 0)
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goto irq_disable;
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if (drm_WARN_ON(&dev_priv->drm, drm_crtc_vblank_get(&crtc->base)))
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goto irq_disable;
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/*
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* Wait for psr to idle out after enabling the VBL interrupts
|
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* VBL interrupts will start the PSR exit and prevent a PSR
|
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* re-entry as well.
|
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*/
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intel_psr_wait_for_idle(new_crtc_state);
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local_irq_disable();
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crtc->debug.min_vbl = min;
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crtc->debug.max_vbl = max;
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trace_intel_pipe_update_start(crtc);
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for (;;) {
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/*
|
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* prepare_to_wait() has a memory barrier, which guarantees
|
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* other CPUs can see the task state update by the time we
|
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* read the scanline.
|
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*/
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prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
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scanline = intel_get_crtc_scanline(crtc);
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if (scanline < min || scanline > max)
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break;
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|
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if (!timeout) {
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drm_err(&dev_priv->drm,
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"Potential atomic update failure on pipe %c\n",
|
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pipe_name(crtc->pipe));
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break;
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}
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local_irq_enable();
|
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timeout = schedule_timeout(timeout);
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local_irq_disable();
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}
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finish_wait(wq, &wait);
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|
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drm_crtc_vblank_put(&crtc->base);
|
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|
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/*
|
||||
* On VLV/CHV DSI the scanline counter would appear to
|
||||
* increment approx. 1/3 of a scanline before start of vblank.
|
||||
* The registers still get latched at start of vblank however.
|
||||
* This means we must not write any registers on the first
|
||||
* line of vblank (since not the whole line is actually in
|
||||
* vblank). And unfortunately we can't use the interrupt to
|
||||
* wait here since it will fire too soon. We could use the
|
||||
* frame start interrupt instead since it will fire after the
|
||||
* critical scanline, but that would require more changes
|
||||
* in the interrupt code. So for now we'll just do the nasty
|
||||
* thing and poll for the bad scanline to pass us by.
|
||||
*
|
||||
* FIXME figure out if BXT+ DSI suffers from this as well
|
||||
*/
|
||||
while (need_vlv_dsi_wa && scanline == vblank_start)
|
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scanline = intel_get_crtc_scanline(crtc);
|
||||
|
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crtc->debug.scanline_start = scanline;
|
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crtc->debug.start_vbl_time = ktime_get();
|
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crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc);
|
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|
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trace_intel_pipe_update_vblank_evaded(crtc);
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return;
|
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|
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irq_disable:
|
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local_irq_disable();
|
||||
}
|
||||
|
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#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_VBLANK_EVADE)
|
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static void dbg_vblank_evade(struct intel_crtc *crtc, ktime_t end)
|
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{
|
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u64 delta = ktime_to_ns(ktime_sub(end, crtc->debug.start_vbl_time));
|
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unsigned int h;
|
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|
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h = ilog2(delta >> 9);
|
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if (h >= ARRAY_SIZE(crtc->debug.vbl.times))
|
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h = ARRAY_SIZE(crtc->debug.vbl.times) - 1;
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crtc->debug.vbl.times[h]++;
|
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|
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crtc->debug.vbl.sum += delta;
|
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if (!crtc->debug.vbl.min || delta < crtc->debug.vbl.min)
|
||||
crtc->debug.vbl.min = delta;
|
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if (delta > crtc->debug.vbl.max)
|
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crtc->debug.vbl.max = delta;
|
||||
|
||||
if (delta > 1000 * VBLANK_EVASION_TIME_US) {
|
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drm_dbg_kms(crtc->base.dev,
|
||||
"Atomic update on pipe (%c) took %lld us, max time under evasion is %u us\n",
|
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pipe_name(crtc->pipe),
|
||||
div_u64(delta, 1000),
|
||||
VBLANK_EVASION_TIME_US);
|
||||
crtc->debug.vbl.over++;
|
||||
}
|
||||
}
|
||||
#else
|
||||
static void dbg_vblank_evade(struct intel_crtc *crtc, ktime_t end) {}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* intel_pipe_update_end() - end update of a set of display registers
|
||||
* @new_crtc_state: the new crtc state
|
||||
*
|
||||
* Mark the end of an update started with intel_pipe_update_start(). This
|
||||
* re-enables interrupts and verifies the update was actually completed
|
||||
* before a vblank.
|
||||
*/
|
||||
void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
|
||||
{
|
||||
struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
|
||||
enum pipe pipe = crtc->pipe;
|
||||
int scanline_end = intel_get_crtc_scanline(crtc);
|
||||
u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
|
||||
ktime_t end_vbl_time = ktime_get();
|
||||
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
|
||||
|
||||
if (new_crtc_state->uapi.async_flip)
|
||||
return;
|
||||
|
||||
trace_intel_pipe_update_end(crtc, end_vbl_count, scanline_end);
|
||||
|
||||
/*
|
||||
* Incase of mipi dsi command mode, we need to set frame update
|
||||
* request for every commit.
|
||||
*/
|
||||
if (INTEL_GEN(dev_priv) >= 11 &&
|
||||
intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
|
||||
icl_dsi_frame_update(new_crtc_state);
|
||||
|
||||
/* We're still in the vblank-evade critical section, this can't race.
|
||||
* Would be slightly nice to just grab the vblank count and arm the
|
||||
* event outside of the critical section - the spinlock might spin for a
|
||||
* while ... */
|
||||
if (new_crtc_state->uapi.event) {
|
||||
drm_WARN_ON(&dev_priv->drm,
|
||||
drm_crtc_vblank_get(&crtc->base) != 0);
|
||||
|
||||
spin_lock(&crtc->base.dev->event_lock);
|
||||
drm_crtc_arm_vblank_event(&crtc->base,
|
||||
new_crtc_state->uapi.event);
|
||||
spin_unlock(&crtc->base.dev->event_lock);
|
||||
|
||||
new_crtc_state->uapi.event = NULL;
|
||||
}
|
||||
|
||||
local_irq_enable();
|
||||
|
||||
/* Send VRR Push to terminate Vblank */
|
||||
intel_vrr_send_push(new_crtc_state);
|
||||
|
||||
if (intel_vgpu_active(dev_priv))
|
||||
return;
|
||||
|
||||
if (crtc->debug.start_vbl_count &&
|
||||
crtc->debug.start_vbl_count != end_vbl_count) {
|
||||
drm_err(&dev_priv->drm,
|
||||
"Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
|
||||
pipe_name(pipe), crtc->debug.start_vbl_count,
|
||||
end_vbl_count,
|
||||
ktime_us_delta(end_vbl_time,
|
||||
crtc->debug.start_vbl_time),
|
||||
crtc->debug.min_vbl, crtc->debug.max_vbl,
|
||||
crtc->debug.scanline_start, scanline_end);
|
||||
}
|
||||
|
||||
dbg_vblank_evade(crtc, end_vbl_time);
|
||||
}
|
||||
|
||||
int intel_plane_check_stride(const struct intel_plane_state *plane_state)
|
||||
{
|
||||
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
|
||||
|
||||
Reference in New Issue
Block a user