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media: i2c: os02g10 update init setting

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Signed-off-by: Yiqing Zeng <zack.zeng@rock-chips.com>
Change-Id: If0465c723970e5027d051eabfc039d9c29c68295
This commit is contained in:
Yiqing Zeng
2021-04-22 11:32:04 +08:00
committed by Tao Huang
parent 63288861f2
commit d513aba573
1 changed files with 52 additions and 36 deletions
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88
drivers/media/i2c/os02g10.c
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@@ -89,7 +89,7 @@
#define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
#define REG_NULL 0xFF
#define REG_DELAY 0x00
#define SENSOR_ID(_msb, _lsb) ((_msb) << 8 | (_lsb))
static const char * const OS02G10_supply_names[] = {
@@ -169,6 +169,11 @@ struct os02g10 {
* Xclk 24Mhz
*/
static const struct regval os02g10_linear10bit_1920x1080_regs[] = {
{0xfd, 0x00},
{0x36, 0x01},
{0xfd, 0x00},
{0x36, 0x00},
{REG_DELAY, 0x05},
{0xfd, 0x00},
{0xfd, 0x00},
{0x30, 0x0a},
@@ -179,10 +184,10 @@ static const struct regval os02g10_linear10bit_1920x1080_regs[] = {
{0xfd, 0x01},
{0x03, 0x04},
{0x04, 0x4c},
{0x06, 0xdd},
{0x24, 0x10},
{0x06, 0x00},
{0x24, 0x30},
{0x01, 0x01},
{0x19, 0x58},
{0x19, 0x50},
{0x1a, 0x0c},
{0x1b, 0x0d},
{0x1c, 0x00},
@@ -191,11 +196,11 @@ static const struct regval os02g10_linear10bit_1920x1080_regs[] = {
{0x22, 0x14},
{0x25, 0x44},
{0x26, 0x0f},
{0x3c, 0xc1},
{0x3d, 0x44},
{0x3c, 0xca},
{0x3d, 0x4a},
{0x40, 0x0f},
{0x43, 0x38},
{0x46, 0x01},
{0x46, 0x00},
{0x47, 0x00},
{0x49, 0x32},
{0x50, 0x01},
@@ -205,20 +210,20 @@ static const struct regval os02g10_linear10bit_1920x1080_regs[] = {
{0x57, 0x16},
{0x59, 0x01},
{0x5a, 0x01},
{0x5d, 0x54},
{0x5d, 0x04},
{0x6a, 0x04},
{0x6b, 0x03},
{0x6e, 0x28},
{0x71, 0xc2},
{0x72, 0x04},
{0x71, 0xbe},
{0x72, 0x06},
{0x73, 0x38},
{0x74, 0x04},
{0x74, 0x06},
{0x79, 0x00},
{0x7a, 0xb2},
{0x7b, 0x10},
{0x8f, 0x80},
{0x91, 0x38},
{0x92, 0x02},
{0x92, 0x0a},
{0x9d, 0x03},
{0x9e, 0x55},
{0xb8, 0x70},
@@ -226,10 +231,14 @@ static const struct regval os02g10_linear10bit_1920x1080_regs[] = {
{0xba, 0x70},
{0xbb, 0x70},
{0xbc, 0x00},
{0xc4, 0x70},
{0xc5, 0x70},
{0xc6, 0x70},
{0xc7, 0x70},
{0xc0, 0x00},
{0xc1, 0x00},
{0xc2, 0x00},
{0xc3, 0x00},
{0xc4, 0x6e},
{0xc5, 0x6e},
{0xc6, 0x6b},
{0xc7, 0x6b},
{0xcc, 0x11},
{0xcd, 0xe0},
{0xd0, 0x1b},
@@ -243,14 +252,18 @@ static const struct regval os02g10_linear10bit_1920x1080_regs[] = {
{0xf1, 0x40},
{0xf2, 0x40},
{0xf3, 0x40},
{0xf4, 0x00},
{0xfa, 0x1c},
{0xfb, 0x33},
{0xfc, 0xff},
{0xfe, 0x01},
{0xfd, 0x03},
{0x03, 0x67},
{0x00, 0x5b},
{0x00, 0x59},
{0x04, 0x11},
{0x05, 0x04},
{0x06, 0x0c},
{0x07, 0x08},
{0x08, 0x08},
{0x09, 0x4f},
{0x0b, 0x08},
@@ -259,15 +272,20 @@ static const struct regval os02g10_linear10bit_1920x1080_regs[] = {
{0xfd, 0x02},
{0x34, 0xfe},
{0x5e, 0x22},
{0xa1, 0x04},
{0xa1, 0x06},
{0xa3, 0x38},
{0xa5, 0x04},
{0xa5, 0x02},
{0xa7, 0x80},
{0xfd, 0x01},
{0xa1, 0x05},
{0x94, 0x44},
{0x95, 0x44},
{0x96, 0x09},
{0x98, 0x44},
{0x9c, 0x0e},
{0xb1, 0x01},
{0xfd, 0x01},
{0xb1, 0x03},
//{0xb1, 0x03},
{REG_NULL, 0x00},
};
@@ -290,11 +308,11 @@ static const struct os02g10_mode supported_modes[] = {
.height = 1080,
.max_fps = {
.numerator = 10000,
.denominator = 250000,
.denominator = 300000,
},
.exp_def = 0x044c,
.hts_def = 0x043a * 2,
.vts_def = 0x0844,
.vts_def = 0x0533,
.reg_list = os02g10_linear10bit_1920x1080_regs,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
@@ -338,14 +356,21 @@ static int os02g10_write_reg(struct i2c_client *client, u8 reg, u8 val)
static int os02g10_write_array(struct i2c_client *client,
const struct regval *regs)
{
int i, ret = 0;
int i, delay_us, ret = 0;
i = 0;
while (regs[i].addr != REG_NULL) {
ret = os02g10_write_reg(client, regs[i].addr, regs[i].val);
if (ret) {
dev_err(&client->dev, "%s failed !\n", __func__);
break;
if (regs[i].addr == REG_DELAY) {
if (regs[i].val) {
delay_us = regs[i].val * 1000;
usleep_range(delay_us, 2 * delay_us);
}
} else {
ret = os02g10_write_reg(client, regs[i].addr, regs[i].val);
if (ret) {
dev_err(&client->dev, "%s failed !\n", __func__);
break;
}
}
i++;
}
@@ -712,15 +737,6 @@ static int __os02g10_start_stream(struct os02g10 *os02g10)
{
int ret;
ret = os02g10_write_reg(os02g10->client, 0xfd, 0x00);
ret |= os02g10_write_reg(os02g10->client, 0x36, 0x01);
ret |= os02g10_write_reg(os02g10->client, 0xfd, 0x00);
ret |= os02g10_write_reg(os02g10->client, 0x36, 0x00);
ret |= os02g10_write_reg(os02g10->client, 0xfd, 0x00);
ret |= os02g10_write_reg(os02g10->client, 0x20, 0x00);
usleep_range(5000, 6000);
ret = os02g10_write_array(os02g10->client, os02g10->cur_mode->reg_list);
if (ret)
return ret;