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rk3066: fix clk_sel10 register error

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Signed-off-by: wdc <wdc@rock-chips.com>
This commit is contained in:
wdc
2014-08-28 19:23:48 +08:00
parent 4145485ccc
commit d575ec606e
2 changed files with 16 additions and 15 deletions
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20
arch/arm/boot/dts/rk3036-clocks.dtsi
View File

@@ -1174,7 +1174,7 @@
"clk_cryto", "clk_i2s_out",
"clk_i2s", "clk_testout";
rockchip,suspend-clkgating-setting=<0xe600 0xe600>;
rockchip,suspend-clkgating-setting=<0x19ff 0x19ff>;
#clock-cells = <1>;
};
@@ -1208,7 +1208,7 @@
"clk_uart2_div", "uart2_frac",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x0F78 0x0F78>;
rockchip,suspend-clkgating-setting=<0xf087 0xf087>;
#clock-cells = <1>;
};
@@ -1240,7 +1240,7 @@
"spdif_frac", "clk_sdio",
"clk_emmc", "reserved";
rockchip,suspend-clkgating-setting=<0x7E40 0x7E40>;
rockchip,suspend-clkgating-setting=<0x81bf 0x81bf>;
#clock-cells = <1>;
};
@@ -1273,7 +1273,7 @@
"hclk_vcodec", "clk_gpu",
"g_hclk_sfc", "reserved";
rockchip,suspend-clkgating-setting=<0x5804 0x5804>;
rockchip,suspend-clkgating-setting=<0xa7fb 0xa7fb>;
#clock-cells = <1>;
};
@@ -1308,7 +1308,7 @@
"g_aclk_intmem", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
rockchip,suspend-clkgating-setting = <0xffff 0xffff>;
#clock-cells = <1>;
};
@@ -1341,7 +1341,7 @@
"reserved", "g_hclk_otg0",
"g_pclk_acodec", "reserved";
rockchip,suspend-clkgating-setting = <0x6e02 0x6e02>;
rockchip,suspend-clkgating-setting = <0x91fd 0x91fd>;
#clock-cells = <1>;
};
@@ -1375,7 +1375,7 @@
"g_hclk_vio_bus", "g_aclk_vio",
"reserved", "reserved";
rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
rockchip,suspend-clkgating-setting = <0xffff 0xffff>;
#clock-cells = <1>;
};
@@ -1409,7 +1409,7 @@
"g_pclk_spi", "reserved",
"reserved", "g_pclk_wdt";
rockchip,suspend-clkgating-setting = <0x900d 0x900d>;
rockchip,suspend-clkgating-setting = <0x6ff2 0x6ff2>;
#clock-cells = <1>;
};
@@ -1443,7 +1443,7 @@
"reserved", "reserved",
"reserved", "reserved";
rockchip,suspend-clkgating-setting=<0x0c73 0x0c73>;
rockchip,suspend-clkgating-setting=<0xf38c 0xf38c>;
#clock-cells = <1>;
};
@@ -1476,7 +1476,7 @@
"reserved", "g_hclk_usb_peri",
"g_hclk_pe_arbi", "g_aclk_peri_niu";
rockchip,suspend-clkgating-setting=<0x2060 0x2060>;
rockchip,suspend-clkgating-setting=<0xdf9f 0xdf9f>;
#clock-cells = <1>;
};

11
arch/arm/mach-rockchip/rk3036.c
View File

@@ -261,7 +261,7 @@ static u32 clk_ungt_save[RK3036_CRU_CLKGATES_CON_CNT];
/*first clk gating value saveing*/
static u32 *p_rkpm_clkgt_last_set;
#define CLK_MSK_GATING(msk, con) cru_writel((0xffff << 16) | msk, con)
#define CLK_MSK_GATING(msk, con) cru_writel((msk << 16) | 0xffff, con)
#define CLK_MSK_UNGATING(msk, con) cru_writel(((~msk) << 16) | 0xffff, con)
static void gtclks_suspend(void)
@@ -271,7 +271,7 @@ static void gtclks_suspend(void)
for (i = 0; i < RK3036_CRU_CLKGATES_CON_CNT; i++) {
clk_ungt_save[i] = cru_readl(RK3036_CRU_CLKGATES_CON(i));
if (i != 10)
CLK_MSK_GATING(clk_ungt_msk[i]
CLK_MSK_UNGATING(clk_ungt_msk[i]
, RK3036_CRU_CLKGATES_CON(i));
else
cru_writel(clk_ungt_msk[i], RK3036_CRU_CLKGATES_CON(i));
@@ -372,6 +372,7 @@ static inline void plls_resume(u32 pll_id)
cru_writel(pllcon1 | 0xf5ff0000, RK3036_PLL_CONS(pll_id, 1));
cru_writel(pllcon2, RK3036_PLL_CONS(pll_id, 2));
pll_udelay(5);
pll_udelay(168);
@@ -417,8 +418,8 @@ static void pm_plls_suspend(void)
gpio0_pin_data = gpio0_readl(0x0);
gpio0_pin_dir = gpio0_readl(0x04);
gpio0_writel(gpio0_pin_dir|0x2, 0x04);
gpio0_writel(gpio0_pin_data|0x2, 0x00);
gpio0_writel(gpio0_pin_dir | 0x2, 0x04);
gpio0_writel(gpio0_pin_data | 0x2, 0x00);
}
static void pm_plls_resume(void)
@@ -436,7 +437,7 @@ static void pm_plls_resume(void)
plls_resume(APLL_ID);
cru_writel(cru_mode_con | (RK3036_PLL_MODE_MSK(APLL_ID) << 16)
, RK3036_CRU_MODE_CON);
cru_writel(clk_sel1 | (CRU_W_MSK(0, 0x1f) | CRU_W_MSK(8, 0x3)
cru_writel(clk_sel10 | (CRU_W_MSK(0, 0x1f) | CRU_W_MSK(8, 0x3)
| CRU_W_MSK(12, 0x3)), RK3036_CRU_CLKSELS_CON(10));
plls_resume(GPLL_ID);
cru_writel(cru_mode_con | (RK3036_PLL_MODE_MSK(GPLL_ID)