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FROMGIT: dt-bindings: phy: realtek: Add Realtek DHC RTD SoC USB 2.0 PHY

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Document the USB PHY bindings for Realtek SoCs.
Realtek DHC (digital home center) RTD SoCs support DWC3 XHCI USB
controller and using USB 2.0 PHY transceiver.

Signed-off-by: Stanley Chang <stanley_chang@realtek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230725033318.8361-4-stanley_chang@realtek.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

Bug: 286930662
(cherry picked from commit 612ad27a30
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git usb-next)
Change-Id: I338ac63f15c10687d79b98a6c68f8901b07869a5
Signed-off-by: Stanley Chang <stanley_chang@realtek.com>
This commit is contained in:
Stanley Chang
2023-05-25 10:21:37 +08:00
committed by Matthias Männich
parent 6e97af079d
commit d58cdad855
1 changed files with 175 additions and 0 deletions
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Documentation/devicetree/bindings/phy/realtek,usb2phy.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2023 Realtek Semiconductor Corporation
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/realtek,usb2phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Realtek DHC SoCs USB 2.0 PHY
maintainers:
- Stanley Chang <stanley_chang@realtek.com>
description: |
Realtek USB 2.0 PHY support the digital home center (DHC) RTD series SoCs.
The USB 2.0 PHY driver is designed to support the XHCI controller. The SoCs
support multiple XHCI controllers. One PHY device node maps to one XHCI
controller.
RTD1295/RTD1619 SoCs USB
The USB architecture includes three XHCI controllers.
Each XHCI maps to one USB 2.0 PHY and map one USB 3.0 PHY on some
controllers.
XHCI controller#0 -- usb2phy -- phy#0
|- usb3phy -- phy#0
XHCI controller#1 -- usb2phy -- phy#0
XHCI controller#2 -- usb2phy -- phy#0
|- usb3phy -- phy#0
RTD1395 SoCs USB
The USB architecture includes two XHCI controllers.
The controller#0 has one USB 2.0 PHY. The controller#1 includes two USB 2.0
PHY.
XHCI controller#0 -- usb2phy -- phy#0
XHCI controller#1 -- usb2phy -- phy#0
|- phy#1
RTD1319/RTD1619b SoCs USB
The USB architecture includes three XHCI controllers.
Each XHCI maps to one USB 2.0 PHY and map one USB 3.0 PHY on controllers#2.
XHCI controller#0 -- usb2phy -- phy#0
XHCI controller#1 -- usb2phy -- phy#0
XHCI controller#2 -- usb2phy -- phy#0
|- usb3phy -- phy#0
RTD1319d SoCs USB
The USB architecture includes three XHCI controllers.
Each xhci maps to one USB 2.0 PHY and map one USB 3.0 PHY on controllers#0.
XHCI controller#0 -- usb2phy -- phy#0
|- usb3phy -- phy#0
XHCI controller#1 -- usb2phy -- phy#0
XHCI controller#2 -- usb2phy -- phy#0
RTD1312c/RTD1315e SoCs USB
The USB architecture includes three XHCI controllers.
Each XHCI maps to one USB 2.0 PHY.
XHCI controller#0 -- usb2phy -- phy#0
XHCI controller#1 -- usb2phy -- phy#0
XHCI controller#2 -- usb2phy -- phy#0
properties:
compatible:
enum:
- realtek,rtd1295-usb2phy
- realtek,rtd1312c-usb2phy
- realtek,rtd1315e-usb2phy
- realtek,rtd1319-usb2phy
- realtek,rtd1319d-usb2phy
- realtek,rtd1395-usb2phy
- realtek,rtd1395-usb2phy-2port
- realtek,rtd1619-usb2phy
- realtek,rtd1619b-usb2phy
reg:
items:
- description: PHY data registers
- description: PHY control registers
"#phy-cells":
const: 0
nvmem-cells:
maxItems: 2
description:
Phandles to nvmem cell that contains the trimming data.
If unspecified, default value is used.
nvmem-cell-names:
items:
- const: usb-dc-cal
- const: usb-dc-dis
description:
The following names, which correspond to each nvmem-cells.
usb-dc-cal is the driving level for each phy specified via efuse.
usb-dc-dis is the disconnection level for each phy specified via efuse.
realtek,inverse-hstx-sync-clock:
description:
For one of the phys of RTD1619b SoC, the synchronous clock of the
high-speed tx must be inverted.
type: boolean
realtek,driving-level:
description:
Control the magnitude of High speed Dp/Dm output swing (mV).
For a different board or port, the original magnitude maybe not meet
the specification. In this situation we can adjust the value to meet
the specification.
$ref: /schemas/types.yaml#/definitions/uint32
default: 8
minimum: 0
maximum: 31
realtek,driving-level-compensate:
description:
For RTD1315e SoC, the driving level can be adjusted by reading the
efuse table. This property provides drive compensation.
If the magnitude of High speed Dp/Dm output swing still not meet the
specification, then we can set this value to meet the specification.
$ref: /schemas/types.yaml#/definitions/int32
default: 0
minimum: -8
maximum: 8
realtek,disconnection-compensate:
description:
This adjusts the disconnection level compensation for the different
boards with different disconnection level.
$ref: /schemas/types.yaml#/definitions/int32
default: 0
minimum: -8
maximum: 8
required:
- compatible
- reg
- "#phy-cells"
allOf:
- if:
not:
properties:
compatible:
contains:
enum:
- realtek,rtd1619b-usb2phy
then:
properties:
realtek,inverse-hstx-sync-clock: false
- if:
not:
properties:
compatible:
contains:
enum:
- realtek,rtd1315e-usb2phy
then:
properties:
realtek,driving-level-compensate: false
additionalProperties: false
examples:
- |
usb-phy@13214 {
compatible = "realtek,rtd1619b-usb2phy";
reg = <0x13214 0x4>, <0x28280 0x4>;
#phy-cells = <0>;
nvmem-cells = <&otp_usb_port0_dc_cal>, <&otp_usb_port0_dc_dis>;
nvmem-cell-names = "usb-dc-cal", "usb-dc-dis";
realtek,inverse-hstx-sync-clock;
realtek,driving-level = <0xa>;
realtek,disconnection-compensate = <(-1)>;
};