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arm: dts: odroidxu3: Enable per cpu thermal trips
1. Each A15 cores thermal sensor now correctly used and will trigger the fan or passive throttling as required. 2. Separate file used for trip points to allow unique labels per trip per cpu to be generated without having to duplicate the trips each time. Keeps code clear and allows for easy changes. 3. Trip points tweaked to optimise performance. A7's kept at full speed for longer since they contribute little to the thermal load. Efficiency is improved by not throttling them until required. A15's throttled earlier to manage performance better under heavy loads to extract maximum performance from the available cooling.
This commit is contained in:
DarkBahamut
@@ -64,7 +64,7 @@
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cooling-min-state = <0>;
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cooling-max-state = <3>;
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#cooling-cells = <2>;
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cooling-levels = <0 150 190 252>;
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cooling-levels = <0 110 170 230>;
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};
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mali: mali@0x11800000 {
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@@ -107,90 +107,28 @@
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thermal-zones {
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cpu0_thermal: cpu0-thermal {
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thermal-sensors = <&tmu_cpu0 0 &tmu_cpu1 0 &tmu_cpu2 0 &tmu_cpu3 0>;
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polling-delay-passive = <250>;
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polling-delay = <1000>;
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trips {
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cpu_alert0: cpu-alert-0 {
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temperature = <70000>; /* millicelsius */
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hysteresis = <10000>; /* millicelsius */
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type = "passive";
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};
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cpu_alert1: cpu-alert-1 {
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temperature = <75000>; /* millicelsius */
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hysteresis = <10000>; /* millicelsius */
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type = "passive";
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};
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cpu_alert2: cpu-alert-2 {
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temperature = <80000>; /* millicelsius */
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hysteresis = <10000>; /* millicelsius */
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type = "passive";
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};
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cpu_alert3: cpu-alert-3 {
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temperature = <90000>; /* millicelsius */
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hysteresis = <10000>; /* millicelsius */
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type = "passive";
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};
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cpu_alert4: cpu-alert-4 {
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temperature = <95000>; /* millicelsius */
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hysteresis = <10000>; /* millicelsius */
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type = "passive";
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};
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cpu_alert5: cpu-alert-5 {
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temperature = <103000>; /* millicelsius */
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hysteresis = <10000>; /* millicelsius */
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type = "passive";
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};
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cpu_alert6: cpu-alert-6 {
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temperature = <110000>; /* millicelsius */
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hysteresis = <10000>; /* millicelsius */
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type = "passive";
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};
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cpu_criti0: cpu-crit-0 {
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temperature = <115000>; /* millicelsius */
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hysteresis = <10000>; /* millicelsius */
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&cpu_alert0>;
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cooling-device = <&fan0 0 1>;
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};
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map1 {
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trip = <&cpu_alert1>;
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cooling-device = <&fan0 1 2>;
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};
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map2 {
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trip = <&cpu_alert2>;
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cooling-device = <&fan0 2 3>;
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};
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/*
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* First trip for A7: 1000Mhz
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* First trip for A15: 1400Mhz
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*/
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map3 {
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trip = <&cpu_alert3>;
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cooling-device = <&cpu0 0 6>;
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};
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map4 {
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trip = <&cpu_alert3>;
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cooling-device = <&cpu4 0 3>;
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};
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/*
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* Second trip for A15: 600Mhz
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* Second trip for A7: 600Mhz
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*/
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map5 {
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trip = <&cpu_alert4>;
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cooling-device = <&cpu0 3 7>;
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};
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map6 {
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trip = <&cpu_alert4>;
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cooling-device = <&cpu4 3 14>;
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};
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};
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thermal-sensors = <&tmu_cpu0 0>;
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#define CPU_THERMAL_ZONE_NUM 0
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#include "exynos5422-odroidxu3-trip-points.dtsi"
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#undef CPU_THERMAL_ZONE_NUM
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};
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cpu1_thermal: cpu1-thermal {
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thermal-sensors = <&tmu_cpu1 0>;
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#define CPU_THERMAL_ZONE_NUM 1
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#include "exynos5422-odroidxu3-trip-points.dtsi"
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#undef CPU_THERMAL_ZONE_NUM
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};
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cpu2_thermal: cpu2-thermal {
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thermal-sensors = <&tmu_cpu2 0>;
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#define CPU_THERMAL_ZONE_NUM 2
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#include "exynos5422-odroidxu3-trip-points.dtsi"
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#undef CPU_THERMAL_ZONE_NUM
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};
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cpu3_thermal: cpu3-thermal {
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thermal-sensors = <&tmu_cpu3 0>;
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#define CPU_THERMAL_ZONE_NUM 3
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#include "exynos5422-odroidxu3-trip-points.dtsi"
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#undef CPU_THERMAL_ZONE_NUM
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};
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};
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};
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100
arch/arm/boot/dts/exynos5422-odroidxu3-trip-points.dtsi
Normal file
100
arch/arm/boot/dts/exynos5422-odroidxu3-trip-points.dtsi
Normal file
@@ -0,0 +1,100 @@
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/*
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* Device tree sources for default OdroidXU3/Exynos5422 thermal zone definition
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*
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* Copyright (c) 2015 Lukasz Majewski <l.majewski@samsung.com>
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* Anand Moon <linux.amoon@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#define _TOKENPASTE(x, y) x ## y
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#define TOKENPASTE(x, y) _TOKENPASTE(x, y)
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#define UNIQIFY(label) TOKENPASTE(label, CPU_THERMAL_ZONE_NUM)
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polling-delay-passive = <250>;
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polling-delay = <1000>;
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trips {
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UNIQIFY(cpu_alert0): cpu-alert-0 {
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temperature = <70000>; /* millicelsius */
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hysteresis = <10000>; /* millicelsius */
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type = "active";
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};
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UNIQIFY(cpu_alert1): cpu-alert-1 {
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temperature = <75000>; /* millicelsius */
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hysteresis = <10000>; /* millicelsius */
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type = "active";
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};
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UNIQIFY(cpu_alert2): cpu-alert-2 {
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temperature = <80000>; /* millicelsius */
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hysteresis = <10000>; /* millicelsius */
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type = "active";
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};
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UNIQIFY(cpu_alert3): cpu-alert-3 {
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temperature = <85000>; /* millicelsius */
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hysteresis = <3000>; /* millicelsius */
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type = "passive";
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};
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UNIQIFY(cpu_alert4): cpu-alert-4 {
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temperature = <90000>; /* millicelsius */
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hysteresis = <3000>; /* millicelsius */
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type = "passive";
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};
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UNIQIFY(cpu_alert5): cpu-alert-5 {
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temperature = <95000>; /* millicelsius */
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hysteresis = <3000>; /* millicelsius */
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type = "passive";
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};
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UNIQIFY(cpu_criti0): cpu-crit-0 {
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temperature = <115000>; /* millicelsius */
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hysteresis = <3000>; /* millicelsius */
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&UNIQIFY(cpu_alert0)>;
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cooling-device = <&fan0 0 1>;
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};
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map1 {
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trip = <&UNIQIFY(cpu_alert1)>;
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cooling-device = <&fan0 1 2>;
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};
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map2 {
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trip = <&UNIQIFY(cpu_alert2)>;
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cooling-device = <&fan0 2 3>;
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};
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/*
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* When reaching cpu_alert3, reduce A15 cores by 1 step.
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* The 2GHz step causes high thermals on multithreaded workloads
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* so better performance is gained by managing it out early.
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*/
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map3 {
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trip = <&UNIQIFY(cpu_alert3)>;
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cooling-device = <&cpu4 0 1>;
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};
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/*
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* When reaching cpu_alert4, reduce A15 cores by 3 steps
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* to further manage the performance level while keeping
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* thermals under control.
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*/
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map4 {
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trip = <&UNIQIFY(cpu_alert4)>;
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cooling-device = <&cpu4 2 4>;
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};
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/*
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* When reaching cpu_alert5, reduce all CPUs to ensure thermal
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* safety. A7 cores don't produce much thermal load so they are
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* reduced less to optimise performance.
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*/
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map5 {
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trip = <&UNIQIFY(cpu_alert5)>;
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cooling-device = <&cpu0 0 2>;
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};
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map6 {
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trip = <&UNIQIFY(cpu_alert5)>;
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cooling-device = <&cpu4 5 14>;
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};
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};
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