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rk3288: set RK3288_LIMIT_PLL_VIO1 to 410MHZ

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dkl
2014-04-30 09:23:30 +08:00
parent f52cfbfccb
commit d64a67250b
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/rockchip/clk-ops.c
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@@ -616,7 +616,7 @@ const struct clk_ops clkops_rate_3288_dclk_lcdc0 = {
.recalc_rate = clk_divider_recalc_rate,
};
#define RK3288_LIMIT_PLL_VIO1 (348*MHZ)
#define RK3288_LIMIT_PLL_VIO1 (410*MHZ)
static long clk_3288_dclk_lcdc1_determine_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *best_parent_rate,