shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-08 03:40:35 +09:00
Code Issues Packages Projects Releases Wiki Activity

usb: optimize g12a & g12b usb phy pll setting.

Browse Source 
PD#173475: usb: optimize g12a & g12b usb phy pll setting.

Change-Id: Iaf2058849d9a112fbcc0e99cab38a65cf6efbd9a
Signed-off-by: Yue Wang <yue.wang@amlogic.com>
This commit is contained in:
Yue Wang
2018-09-11 14:19:42 +08:00
committed by Jianxin Pan
parent 1fef1fae05
commit d65d69a6ad
2 changed files with 3 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm64/boot/dts/amlogic/mesong12a.dtsi
View File

@@ -384,7 +384,7 @@
pll-setting-3 = <0xac5f49e5>;
pll-setting-4 = <0xfe18>;
pll-setting-5 = <0xfff>;
pll-setting-6 = <0xc8000>;
pll-setting-6 = <0x78000>;
pll-setting-7 = <0xe0004>;
pll-setting-8 = <0xe000c>;
};

4
arch/arm64/boot/dts/amlogic/mesong12b.dtsi
View File

@@ -421,10 +421,10 @@
0x0 0xff63a000 0x0 0x2000>;
pll-setting-1 = <0x09400414>;
pll-setting-2 = <0x927E0000>;
pll-setting-3 = <0xac5f49e5>;
pll-setting-3 = <0xac5f69e5>;
pll-setting-4 = <0xfe18>;
pll-setting-5 = <0xfff>;
pll-setting-6 = <0xc8000>;
pll-setting-6 = <0x78000>;
pll-setting-7 = <0xe0004>;
pll-setting-8 = <0xe000c>;
};