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clk: rockchip: rk3308: Fix spi clock's name

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Change-Id: Id15d23786eed3e0105ad4f53858421a222e680d9
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This commit is contained in:
Finley Xiao
2018-09-21 15:11:23 +08:00
parent 7b544df052
commit d66b155307
1 changed files with 3 additions and 3 deletions
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6
drivers/clk/rockchip/clk-rk3308.c
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@@ -414,13 +414,13 @@ static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = {
RK3308_CLKSEL_CON(75), 14, 2, MFLAGS, 0, 7, DFLAGS,
RK3308_CLKGATE_CON(15), 1, GFLAGS),
COMPOSITE(SCLK_SPI0, "clk_isp0", mux_dpll_vpll0_xin24m_p, 0,
COMPOSITE(SCLK_SPI0, "clk_spi0", mux_dpll_vpll0_xin24m_p, 0,
RK3308_CLKSEL_CON(30), 14, 2, MFLAGS, 0, 7, DFLAGS,
RK3308_CLKGATE_CON(3), 2, GFLAGS),
COMPOSITE(SCLK_SPI1, "clk_isp1", mux_dpll_vpll0_xin24m_p, 0,
COMPOSITE(SCLK_SPI1, "clk_spi1", mux_dpll_vpll0_xin24m_p, 0,
RK3308_CLKSEL_CON(31), 14, 2, MFLAGS, 0, 7, DFLAGS,
RK3308_CLKGATE_CON(3), 3, GFLAGS),
COMPOSITE(SCLK_SPI2, "clk_isp2", mux_dpll_vpll0_xin24m_p, 0,
COMPOSITE(SCLK_SPI2, "clk_spi2", mux_dpll_vpll0_xin24m_p, 0,
RK3308_CLKSEL_CON(32), 14, 2, MFLAGS, 0, 7, DFLAGS,
RK3308_CLKGATE_CON(3), 4, GFLAGS),