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drm/rockchip: vop2: fix overlay mode config error for port1/2

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Change-Id: I213a78641bfb1a75d492e24fe3ca3118bc8fce48
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
This commit is contained in:
Sandy Huang
2020-11-23 11:58:45 +08:00
parent da821f36d7
commit d6d6ab6a93
1 changed files with 2 additions and 2 deletions
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4
drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
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@@ -406,7 +406,7 @@ static const struct vop2_video_port_regs rk3568_vop_vp0_regs = {
static const struct vop2_video_port_regs rk3568_vop_vp1_regs = {
.cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 1),
.overlay_mode = VOP_REG(RK3568_OVL_CTRL, 0x1, 0),
.overlay_mode = VOP_REG(RK3568_OVL_CTRL, 0x1, 1),
.port_mux = VOP_REG(RK3568_OVL_PORT_SEL, 0xf, 4),
.out_mode = VOP_REG(RK3568_VP1_DSP_CTRL, 0xf, 0),
.standby = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 31),
@@ -438,7 +438,7 @@ static const struct vop2_video_port_regs rk3568_vop_vp1_regs = {
static const struct vop2_video_port_regs rk3568_vop_vp2_regs = {
.cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 2),
.overlay_mode = VOP_REG(RK3568_OVL_CTRL, 0x1, 0),
.overlay_mode = VOP_REG(RK3568_OVL_CTRL, 0x1, 2),
.port_mux = VOP_REG(RK3568_OVL_PORT_SEL, 0xf, 8),
.out_mode = VOP_REG(RK3568_VP2_DSP_CTRL, 0xf, 0),
.standby = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 31),