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media: rockchip: isp: fix normal merge enable config

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RKISP_NORMAL_MERGE_EN default 1 to enable this function

Change-Id: Iccb33ba372baa90306329998fd64f872063b7609
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
This commit is contained in:
Cai YiWei
2020-11-06 13:33:33 +08:00
committed by Tao Huang
parent a9a31fbbc5
commit d760ab0140
4 changed files with 95 additions and 29 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/media/platform/rockchip/isp/common.h
View File

@@ -63,6 +63,8 @@
#define RKISP_EMDDATA_FIFO_MAX 4
#define RKISP_DMATX_CHECK 0xA5A5A5A5
#define RKISP_NORMAL_MERGE_EN 1
struct rkisp_device;
/* ISP_V10_1 for only support MP */

89
drivers/media/platform/rockchip/isp/csi.c
View File

@@ -13,6 +13,54 @@
#include "dev.h"
#include "regs.h"
static void __maybe_unused fixed_normal_merge_config(struct rkisp_device *dev)
{
struct rkisp_stream *stream;
int i;
if (dev->isp_ver != ISP_V20 &&
dev->csi_dev.rd_mode != HDR_RDBK_FRAME1)
return;
stream = &dev->dmarx_dev.stream[RKISP_STREAM_RAWRD2];
if (stream->curr_buf)
rkisp_write(dev, MI_RAW0_RD_BASE,
stream->curr_buf->buff_addr[0], false);
rkisp_write(dev, MI_RAW0_RD_LENGTH,
rkisp_read(dev, MI_RAW2_RD_LENGTH, false), false);
rkisp_write(dev, ISP_HDRMGE_BASE, SW_HDRMGE_EN |
SW_HDRMGE_MODE_FRAMEX2, false);
rkisp_write(dev, ISP_HDRMGE_GAIN0, 0xfff0040, false);
rkisp_write(dev, ISP_HDRMGE_GAIN1, 0xfff0040, false);
rkisp_write(dev, ISP_HDRMGE_GAIN2, 0x40, false);
rkisp_write(dev, ISP_HDRMGE_CONS_DIFF, 0x26e626cd, false);
for (i = ISP_HDRMGE_DIFF_Y0; i <= ISP_HDRMGE_DIFF_Y3; i += 4)
rkisp_write(dev, i, 0, false);
rkisp_write(dev, ISP_HDRMGE_DIFF_Y4, 0x10001, false);
rkisp_write(dev, ISP_HDRMGE_DIFF_Y5, 0x40004, false);
rkisp_write(dev, ISP_HDRMGE_DIFF_Y6, 0xd000d, false);
rkisp_write(dev, ISP_HDRMGE_DIFF_Y7, 0x2b002b, false);
rkisp_write(dev, ISP_HDRMGE_DIFF_Y8, 0x890089, false);
rkisp_write(dev, ISP_HDRMGE_DIFF_Y9, 0x1680168, false);
rkisp_write(dev, ISP_HDRMGE_DIFF_Y10, 0x29e029e, false);
rkisp_write(dev, ISP_HDRMGE_DIFF_Y11, 0x3790379, false);
rkisp_write(dev, ISP_HDRMGE_DIFF_Y12, 0x3d603d6, false);
rkisp_write(dev, ISP_HDRMGE_DIFF_Y13, 0x3f303f3, false);
rkisp_write(dev, ISP_HDRMGE_DIFF_Y14, 0x3fc03fc, false);
rkisp_write(dev, ISP_HDRMGE_DIFF_Y15, 0x3ff03ff, false);
rkisp_write(dev, ISP_HDRMGE_DIFF_Y16, 0x3ff03ff, false);
for (i = ISP_HDRMGE_OVER_Y0; i <= ISP_HDRMGE_OVER_Y7; i += 4)
rkisp_write(dev, i, 0, false);
rkisp_write(dev, ISP_HDRMGE_OVER_Y8, 0x4, false);
rkisp_write(dev, ISP_HDRMGE_OVER_Y9, 0x2a, false);
rkisp_write(dev, ISP_HDRMGE_OVER_Y10, 0x162, false);
rkisp_write(dev, ISP_HDRMGE_OVER_Y11, 0x376, false);
rkisp_write(dev, ISP_HDRMGE_OVER_Y12, 0x3f3, false);
for (i = ISP_HDRMGE_OVER_Y12; i <= ISP_HDRMGE_OVER_Y16; i += 4)
rkisp_write(dev, i, 0x3ff, false);
}
static void get_remote_mipi_sensor(struct rkisp_device *dev,
struct v4l2_subdev **sensor_sd, u32 function)
{
@@ -322,7 +370,6 @@ static int csi_config(struct rkisp_csi_device *csi)
/* hdr merge */
switch (dev->hdr.op_mode) {
case HDR_RDBK_FRAME1:
case HDR_RDBK_FRAME2:
case HDR_FRAMEX2_DDR:
case HDR_LINEX2_DDR:
@@ -437,8 +484,7 @@ int rkisp_csi_config_patch(struct rkisp_device *dev)
}
}
if (dev->hdr.op_mode == HDR_RDBK_FRAME2 ||
dev->hdr.op_mode == HDR_RDBK_FRAME1)
if (dev->hdr.op_mode == HDR_RDBK_FRAME2)
val = SW_HDRMGE_EN | SW_HDRMGE_MODE_FRAMEX2;
else if (dev->hdr.op_mode == HDR_RDBK_FRAME3)
val = SW_HDRMGE_EN | SW_HDRMGE_MODE_FRAMEX3;
@@ -454,6 +500,15 @@ int rkisp_csi_config_patch(struct rkisp_device *dev)
dev->csi_dev.rd_mode = dev->hdr.op_mode;
rkisp_set_bits(dev, CTRL_SWS_CFG,
0, SW_MPIP_DROP_FRM_DIS, true);
#if RKISP_NORMAL_MERGE_EN
if (!dev->hw_dev->is_mi_update &&
dev->hdr.op_mode == HDR_RDBK_FRAME1 &&
dev->isp_ver == ISP_V20)
rkisp_write(dev, CSI2RX_CTRL0,
SW_IBUF_OP_MODE(HDR_RDBK_FRAME2) |
SW_HDR_ESP_MODE(dev->hdr.esp_mode), true);
fixed_normal_merge_config(dev);
#endif
}
dev->csi_dev.frame_cnt = -1;
dev->csi_dev.frame_cnt_x1 = -1;
@@ -485,13 +540,15 @@ void rkisp_trigger_read_back(struct rkisp_csi_device *csi, u8 dma2frm, u32 mode)
else
csi->frame_cnt_x1++;
csi->frame_cnt++;
/* configure hdr params in rdbk mode */
rkisp_params_cfg(params_vdev, cur_frame_id, dma2frm + 1);
val = 0;
if (mode & T_START_X1) {
csi->rd_mode = HDR_RDBK_FRAME1;
val = SW_HDRMGE_EN | SW_HDRMGE_MODE_FRAMEX2;
#if RKISP_NORMAL_MERGE_EN
fixed_normal_merge_config(dev);
if (dev->isp_ver == ISP_V20)
val = SW_HDRMGE_EN | SW_HDRMGE_MODE_FRAMEX2;
#endif
} else if (mode & T_START_X2) {
csi->rd_mode = HDR_RDBK_FRAME2;
val = SW_HDRMGE_EN | SW_HDRMGE_MODE_FRAMEX2;
@@ -506,6 +563,8 @@ void rkisp_trigger_read_back(struct rkisp_csi_device *csi, u8 dma2frm, u32 mode)
dev->skip_frame = 2;
is_upd = true;
}
/* configure hdr params in rdbk mode */
rkisp_params_cfg(params_vdev, cur_frame_id, dma2frm + 1);
if (!hw->is_single) {
rkisp_update_regs(dev, CTRL_VI_ISP_PATH, SUPER_IMP_COLOR_CR);
@@ -522,16 +581,18 @@ void rkisp_trigger_read_back(struct rkisp_csi_device *csi, u8 dma2frm, u32 mode)
/* wait 50 us to load lsc table, otherwise lsc lut error will occur */
udelay(50);
}
v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev,
"readback frame:%d time:%d\n",
cur_frame_id, dma2frm + 1);
val = rkisp_read(dev, CSI2RX_CTRL0, true);
val &= ~SW_IBUF_OP_MODE(0xf);
if (csi->rd_mode == HDR_RDBK_FRAME1)
val |= SW_IBUF_OP_MODE(HDR_RDBK_FRAME2);
else
val |= SW_IBUF_OP_MODE(csi->rd_mode);
val |= SW_CSI2RX_EN | SW_DMA_2FRM_MODE(dma2frm);
tmp = SW_IBUF_OP_MODE(csi->rd_mode);
#if RKISP_NORMAL_MERGE_EN
if (csi->rd_mode == HDR_RDBK_FRAME1 && dev->isp_ver == ISP_V20)
tmp = SW_IBUF_OP_MODE(HDR_RDBK_FRAME2);
#endif
val |= tmp | SW_CSI2RX_EN | SW_DMA_2FRM_MODE(dma2frm);
v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev,
"readback frame:%d time:%d 0x%x\n",
cur_frame_id, dma2frm + 1, val);
rkisp_write(dev, CSI2RX_CTRL0, val, true);
}

26
drivers/media/platform/rockchip/isp/dmarx.c
View File

@@ -346,7 +346,7 @@ static void update_rawrd(struct rkisp_stream *stream)
} else if (dev->dmarx_dev.trigger == T_AUTO) {
/* internal raw wr/rd buf rotate */
struct rkisp_dummy_buffer *buf;
u32 id, rawwr_addr;
u32 id, rawwr_addr, val;
switch (stream->id) {
case RKISP_STREAM_RAWRD2:
@@ -368,22 +368,20 @@ static void update_rawrd(struct rkisp_stream *stream)
}
buf = hdr_dqbuf(&dev->hdr.q_rx[id]);
if (buf) {
mi_set_y_addr(stream, buf->dma_addr);
val = buf->dma_addr;
dev->hdr.rx_cur_buf[id] = buf;
} else {
mi_set_y_addr(stream,
readl(base + rawwr_addr));
val = readl(base + rawwr_addr);
}
}
if (dev->isp_ver == ISP_V20 &&
dev->csi_dev.rd_mode == HDR_RDBK_FRAME1 &&
stream->id == RKISP_STREAM_RAWRD2) {
rkisp_write(dev, MI_RAW0_RD_BASE,
rkisp_read(dev, MI_RAW2_RD_BASE, false),
false);
rkisp_write(dev, MI_RAW0_RD_LENGTH,
rkisp_read(dev, MI_RAW2_RD_LENGTH, false),
false);
mi_set_y_addr(stream, val);
#if RKISP_NORMAL_MERGE_EN
if (dev->isp_ver == ISP_V20 &&
dev->csi_dev.rd_mode == HDR_RDBK_FRAME1) {
rkisp_write(dev, MI_RAW0_RD_BASE, val, true);
rkisp_write(dev, MI_RAW0_RD_LENGTH,
rkisp_read(dev, MI_RAW2_RD_LENGTH, true), true);
}
#endif
}
}

7
drivers/media/platform/rockchip/isp/isp_params_v2x.c
View File

@@ -3432,10 +3432,15 @@ isp_gain_config(struct rkisp_isp_params_vdev *params_vdev,
u32 value, i, gain_wsize;
u8 mge_en;
if (dev->csi_dev.rd_mode != HDR_NORMAL)
if (dev->csi_dev.rd_mode != HDR_NORMAL &&
dev->csi_dev.rd_mode != HDR_RDBK_FRAME1)
mge_en = 1;
else
mge_en = 0;
#if RKISP_NORMAL_MERGE_EN
if (dev->csi_dev.rd_mode == HDR_RDBK_FRAME1)
mge_en = 1;
#endif
gain_wsize = rkisp_ioread32(params_vdev, MI_GAIN_WR_SIZE);
gain_wsize &= 0x0FFFFFF0;