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drm/bridge: synopsys: dw-hdmi-qp: filter hdmi 2.1 resolution when enable-gpio is not configured
Change-Id: I84e6a7f295441c9a9b6ae2cdb897d88c81582480 Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
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@@ -2753,6 +2753,7 @@ dw_hdmi_qp_bridge_mode_valid(struct drm_bridge *bridge,
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const struct drm_display_mode *mode)
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{
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struct dw_hdmi_qp *hdmi = bridge->driver_private;
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const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
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if (mode->clock <= 25000)
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return MODE_CLOCK_RANGE;
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@@ -2760,6 +2761,10 @@ dw_hdmi_qp_bridge_mode_valid(struct drm_bridge *bridge,
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if (!hdmi->sink_is_hdmi && mode->clock > 340000)
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return MODE_BAD;
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if (pdata->mode_valid)
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return pdata->mode_valid(NULL, pdata->priv_data, info,
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mode);
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return MODE_OK;
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}
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@@ -1590,14 +1590,6 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *dw_hdmi, void *data,
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struct drm_crtc *crtc;
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struct rockchip_hdmi *hdmi;
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/*
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* Pixel clocks we support are always < 2GHz and so fit in an
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* int. We should make sure source rate does too so we don't get
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* overflow when we multiply by 1000.
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*/
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if (mode->clock > INT_MAX / 1000)
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return MODE_BAD;
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if (!encoder) {
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const struct drm_connector_helper_funcs *funcs;
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@@ -1614,6 +1606,21 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *dw_hdmi, void *data,
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hdmi = to_rockchip_hdmi(encoder);
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if (hdmi->is_hdmi_qp) {
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if (!hdmi->enable_gpio && mode->clock > 600000)
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return MODE_BAD;
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return MODE_OK;
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}
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/*
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* Pixel clocks we support are always < 2GHz and so fit in an
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* int. We should make sure source rate does too so we don't get
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* overflow when we multiply by 1000.
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*/
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if (mode->clock > INT_MAX / 1000)
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return MODE_BAD;
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/*
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* If sink max TMDS clock < 340MHz, we should check the mode pixel
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* clock > 340MHz is YCbCr420 or not and whether the platform supports
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@@ -3363,6 +3370,7 @@ struct rockchip_hdmi_chip_data rk3588_hdmi_chip_data = {
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};
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static const struct dw_hdmi_plat_data rk3588_hdmi_drv_data = {
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.mode_valid = dw_hdmi_rockchip_mode_valid,
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.phy_data = &rk3588_hdmi_chip_data,
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.qp_phy_ops = &rk3588_hdmi_phy_ops,
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.phy_name = "samsung_hdptx_phy",
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