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Merge commit '6fe07fe66175aa84c7f56d3071be5d7cb730e07b'

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* commit '6fe07fe66175aa84c7f56d3071be5d7cb730e07b':
  pwm: rockchip: enable dclk scale function in oneshot mode
  soc: rockchip_system_monitor: Fix TPYE -> TYPE typo
  media: i2c: max96712: version 1.05.00
  drm/panel: maxim-max96752f: Fix pin assignment
  soc: rockchip: tb_service: unmask mcu_done after all registered cb were finished
  arm64: dts: rockchip: rk3588s: Fix low-volt-mem-read-margin
  arm64: dts: rockchip: rk3588: Fixed the rkvenc1 init frequency
  phy: rockchip: samsung-dcphy: restart rx after apb reset when rx is streaming

Change-Id: I169f5ca13020b86970b62eda17cb6ca50067464d
This commit is contained in:
Tao Huang
2023-06-13 16:23:41 +08:00
parent 04c44c91e5 6fe07fe661
commit d78ed97ebf
17 changed files with 180 additions and 84 deletions
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6
arch/arm64/boot/dts/rockchip/rk3588s.dtsi
View File

@@ -2927,7 +2927,7 @@
675000 3
495000 4
>;
low-volt-read-margin = <4>;
low-volt-mem-read-margin = <4>;
intermediate-threshold-freq = <500000>; /* KHz*/
rockchip,init-freq = <1000000>; /* KHz */
@@ -3463,9 +3463,9 @@
interrupt-names = "irq_rkvenc1";
clocks = <&cru ACLK_RKVENC1>, <&cru HCLK_RKVENC1>, <&cru CLK_RKVENC1_CORE>;
clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
rockchip,normal-rates = <600000000>, <0>, <800000000>;
rockchip,normal-rates = <500000000>, <0>, <800000000>;
assigned-clocks = <&cru ACLK_RKVENC1>, <&cru CLK_RKVENC1_CORE>;
assigned-clock-rates = <600000000>, <800000000>;
assigned-clock-rates = <500000000>, <800000000>;
resets = <&cru SRST_A_RKVENC1>, <&cru SRST_H_RKVENC1>, <&cru SRST_RKVENC1_CORE>;
reset-names = "video_a", "video_h", "video_core";
rockchip,skip-pmu-idle-request;

2
drivers/cpufreq/rockchip-cpufreq.c
View File

@@ -714,7 +714,7 @@ static int rockchip_cpufreq_add_monitor(struct cluster_info *cluster,
if (!mdevp)
return -ENOMEM;
mdevp->type = MONITOR_TPYE_CPU;
mdevp->type = MONITOR_TYPE_CPU;
mdevp->low_temp_adjust = rockchip_monitor_cpu_low_temp_adjust;
mdevp->high_temp_adjust = rockchip_monitor_cpu_high_temp_adjust;
mdevp->update_volt = rockchip_monitor_check_rate_volt;

2
drivers/devfreq/rockchip_dmc.c
View File

@@ -180,7 +180,7 @@ static struct pm_qos_request pm_qos;
static int rockchip_dmcfreq_opp_helper(struct dev_pm_set_opp_data *data);
static struct monitor_dev_profile dmc_mdevp = {
.type = MONITOR_TPYE_DEV,
.type = MONITOR_TYPE_DEV,
.low_temp_adjust = rockchip_monitor_dev_low_temp_adjust,
.high_temp_adjust = rockchip_monitor_dev_high_temp_adjust,
.update_volt = rockchip_monitor_check_rate_volt,

2
drivers/gpu/arm/bifrost/backend/gpu/mali_kbase_devfreq.c
View File

@@ -46,7 +46,7 @@
static struct devfreq_simple_ondemand_data ondemand_data;
static struct monitor_dev_profile mali_mdevp = {
.type = MONITOR_TPYE_DEV,
.type = MONITOR_TYPE_DEV,
.low_temp_adjust = rockchip_monitor_dev_low_temp_adjust,
.high_temp_adjust = rockchip_monitor_dev_high_temp_adjust,
.update_volt = rockchip_monitor_check_rate_volt,

2
drivers/gpu/arm/mali400/mali/linux/mali_devfreq.c
View File

@@ -41,7 +41,7 @@
#include <soc/rockchip/rockchip_system_monitor.h>
static struct monitor_dev_profile mali_mdevp = {
.type = MONITOR_TPYE_DEV,
.type = MONITOR_TYPE_DEV,
.low_temp_adjust = rockchip_monitor_dev_low_temp_adjust,
.high_temp_adjust = rockchip_monitor_dev_high_temp_adjust,
};

2
drivers/gpu/arm/midgard/backend/gpu/mali_kbase_devfreq.c
View File

@@ -51,7 +51,7 @@
static struct devfreq_simple_ondemand_data ondemand_data;
static struct monitor_dev_profile mali_mdevp = {
.type = MONITOR_TPYE_DEV,
.type = MONITOR_TYPE_DEV,
.low_temp_adjust = rockchip_monitor_dev_low_temp_adjust,
.high_temp_adjust = rockchip_monitor_dev_high_temp_adjust,
};

15
drivers/gpu/drm/panel/panel-maxim-max96752f.c
View File

@@ -406,12 +406,11 @@ static int hannstar_hsd123jpw3_a15_prepare(struct max96752f *max96752f)
{
maxim_deserializer_write(max96752f, 0x0002, 0x43);
maxim_deserializer_write(max96752f, 0x0140, 0x20);
maxim_deserializer_write(max96752f, 0x01ce, 0x5e);
maxim_deserializer_write(max96752f, 0x01ce, 0x5e); /* oldi */
maxim_deserializer_write(max96752f, 0x0226, 0x40); /* bl_pwm */
maxim_deserializer_write(max96752f, 0x0224, 0x84);
maxim_deserializer_write(max96752f, 0x0204, 0xa1); /* tp_int */
maxim_deserializer_write(max96752f, 0x0203, 0x83);
maxim_deserializer_write(max96752f, 0x0203, 0x83); /* GPIO1 <- TP_INT */
maxim_deserializer_write(max96752f, 0x0206, 0x84); /* GPIO2 -> TP_RST */
maxim_deserializer_write(max96752f, 0x0224, 0x84); /* GPIO12 -> LCD_BL_PWM */
return 0;
}
@@ -423,8 +422,7 @@ static int hannstar_hsd123jpw3_a15_unprepare(struct max96752f *max96752f)
static int hannstar_hsd123jpw3_a15_enable(struct max96752f *max96752f)
{
maxim_deserializer_write(max96752f, 0x0221, 0x90); /* lcd_rst */
maxim_deserializer_write(max96752f, 0x0206, 0x90); /* tp_rst */
maxim_deserializer_write(max96752f, 0x0221, 0x90); /* GPIO11 -> LCD_RESET */
msleep(20);
return 0;
@@ -432,8 +430,7 @@ static int hannstar_hsd123jpw3_a15_enable(struct max96752f *max96752f)
static int hannstar_hsd123jpw3_a15_disable(struct max96752f *max96752f)
{
maxim_deserializer_write(max96752f, 0x0206, 0x80); /* tp_rst */
maxim_deserializer_write(max96752f, 0x0227, 0x80); /* lcd_rst */
maxim_deserializer_write(max96752f, 0x0221, 0x80); /* GPIO11 -> LCD_RESET */
msleep(20);
return 0;

144
drivers/media/i2c/max96712.c
View File

@@ -15,12 +15,15 @@
* mipi dpll predef rate set api.
* V1.4.00 i2c read/write api update.
* support for GMSL1 Link.
* V1.5.00 only check max96712 chipid when probe.
* enable stream out if not all link are locked.
*
*/
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/iopoll.h>
#include <linux/gpio/consumer.h>
#include <linux/pinctrl/consumer.h>
#include <linux/i2c.h>
@@ -42,7 +45,7 @@
#include <media/v4l2-fwnode.h>
#include <media/v4l2-subdev.h>
#define DRIVER_VERSION KERNEL_VERSION(1, 0x04, 0x00)
#define DRIVER_VERSION KERNEL_VERSION(1, 0x05, 0x00)
#ifndef V4L2_CID_DIGITAL_GAIN
#define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
@@ -76,7 +79,7 @@
#define MAX96712_LOCK_STATE_LINK_D BIT(3)
#define MAX96712_LOCK_STATE_MASK 0x0F /* bit[3:0], GMSL link mask: 1 = disable, 1 = enable */
#define MAX96712_FORCE_ALL_CLOCK_EN 0 /* 1: enable, 0: disable */
#define MAX96712_FORCE_ALL_CLOCK_EN 1 /* 1: enable, 0: disable */
#define REG_NULL 0xFFFF
@@ -473,6 +476,62 @@ static int max96712_write_array(struct i2c_client *client,
return ret;
}
static int max96712_check_local_chipid(struct max96712 *max96712)
{
struct i2c_client *client = max96712->client;
struct device *dev = &max96712->client->dev;
int ret;
u8 id = 0;
ret = max96712_read_reg(client, MAX96712_I2C_ADDR,
MAX96712_REG_CHIP_ID, MAX96712_REG_LENGTH_16BIT,
MAX96712_REG_VALUE_08BIT, &id);
if ((ret != 0) || (id != MAX96712_CHIP_ID)) {
dev_err(dev, "Unexpected MAX96712 chip id(%02x), ret(%d)\n", id, ret);
return -ENODEV;
}
dev_info(dev, "Detected MAX96712 chipid: %02x\n", id);
return 0;
}
static int __maybe_unused max96712_check_remote_chipid(struct max96712 *max96712)
{
struct device *dev = &max96712->client->dev;
int ret = 0;
u8 id;
dev_info(dev, "Check remote chipid\n");
id = 0;
#if 0
// max96717
ret = max96712_read_reg(max96712->client, MAX96717_I2C_ADDR,
MAX96717_REG_CHIP_ID, MAX96712_REG_LENGTH_16BIT,
MAX96712_REG_VALUE_08BIT, &id);
if ((ret != 0) || (id != MAX96717_CHIP_ID)) {
dev_err(dev, "Unexpected MAX96717 chip id(%02x), ret(%d)\n", id, ret);
return -ENODEV;
}
dev_info(dev, "Detected MAX96717 chipid: 0x%02x\n", id);
#endif
#if 0
// max96715
ret = max96712_read_reg(max96712->client, MAX96715_I2C_ADDR,
MAX96715_REG_CHIP_ID, MAX96712_REG_LENGTH_08BIT,
MAX96712_REG_VALUE_08BIT, &id);
if ((ret != 0) || (id != MAX96715_CHIP_ID)) {
dev_err(dev, "Unexpected MAX96715 chip id(%02x), ret(%d)\n", id, ret);
return -ENODEV;
}
dev_info(dev, "Detected MAX96715 chipid: 0x%02x\n", id);
#endif
return ret;
}
static u8 max96712_get_link_lock_state(struct max96712 *max96712, u8 link_mask)
{
struct i2c_client *client = max96712->client;
@@ -577,18 +636,12 @@ static int max96712_check_link_lock_state(struct max96712 *max96712)
{
struct i2c_client *client = max96712->client;
struct device *dev = &max96712->client->dev;
u8 id = 0, lock_state = 0, link_mask = 0, link_type = 0;
u8 lock_state = 0, link_mask = 0, link_type = 0;
int ret, i, time_ms;
ret = max96712_read_reg(client, MAX96712_I2C_ADDR,
MAX96712_REG_CHIP_ID, MAX96712_REG_LENGTH_16BIT,
MAX96712_REG_VALUE_08BIT, &id);
if (id != MAX96712_CHIP_ID) {
dev_err(dev, "Unexpected MAX96712 chip id(%02x), ret(%d)\n", id, ret);
return -ENODEV;
}
dev_info(dev, "Detected MAX96712 chipid: %02x\n", id);
ret = max96712_check_local_chipid(max96712);
if (ret)
return ret;
/* IF VDD = 1.2V: Enable REG_ENABLE and REG_MNL
* CTRL0: Enable REG_ENABLE
@@ -691,26 +744,9 @@ static int max96712_check_link_lock_state(struct max96712 *max96712)
}
if ((lock_state & link_mask) == link_mask) {
dev_info(dev, "All Links are locked: 0x%x\n", lock_state);
dev_info(dev, "All Links are locked: 0x%x, time_ms = %d\n", lock_state, time_ms);
#if 0
ret = max96712_read_reg(client, MAX96717_I2C_ADDR,
MAX96717_REG_CHIP_ID, MAX96712_REG_LENGTH_16BIT,
MAX96712_REG_VALUE_08BIT, &id);
if (id != MAX96717_CHIP_ID) {
dev_err(dev, "Unexpected MAX96717 chip id(%02x), ret(%d)\n", id, ret);
return -ENODEV;
}
dev_info(dev, "Detected MAX96717 chipid: 0x%02x\n", id);
#endif
#if 0
ret = max96712_read_reg(client, MAX96715_I2C_ADDR,
MAX96715_REG_CHIP_ID, MAX96712_REG_LENGTH_08BIT,
MAX96712_REG_VALUE_08BIT, &id);
if (id != MAX96715_CHIP_ID) {
dev_err(dev, "Unexpected MAX96715 chip id(%02x), ret(%d)\n", id, ret);
return -ENODEV;
}
dev_info(dev, "Detected MAX96715 chipid: 0x%02x\n", id);
max96712_check_remote_chipid(max96712);
#endif
return 0;
}
@@ -719,8 +755,13 @@ static int max96712_check_link_lock_state(struct max96712 *max96712)
time_ms += 10;
}
dev_err(dev, "Failed to detect camera link!\n");
return -ENODEV;
if ((lock_state & link_mask) != 0) {
dev_info(dev, "Partial links are locked: 0x%x, time_ms = %d\n", lock_state, time_ms);
return 0;
} else {
dev_err(dev, "Failed to detect camera link, time_ms = %d!\n", time_ms);
return -ENODEV;
}
}
static irqreturn_t max96712_hot_plug_detect_irq_handler(int irq, void *dev_id)
@@ -828,15 +869,24 @@ static int __maybe_unused max96712_dphy_dpll_predef_set(struct i2c_client *clien
MAX96712_REG_VALUE_08BIT, 0xf5);
}
ret |= max96712_read_reg(client, MAX96712_I2C_ADDR,
0x0400, MAX96712_REG_LENGTH_16BIT,
MAX96712_REG_VALUE_08BIT, &dpll_lock);
if (ret)
if (ret) {
dev_err(&client->dev, "DPLL predef set error!\n");
return ret;
}
dev_info(&client->dev, "DPLL predef set: dpll_lock = 0x%02x\n", dpll_lock);
return ret;
ret = read_poll_timeout(max96712_read_reg, ret,
!(ret < 0) && (dpll_lock & 0xF0),
1000, 10000, false,
client, MAX96712_I2C_ADDR,
0x0400, MAX96712_REG_LENGTH_16BIT,
MAX96712_REG_VALUE_08BIT, &dpll_lock);
if (ret < 0) {
dev_err(&client->dev, "DPLL is not locked, dpll_lock = 0x%02x\n", dpll_lock);
return ret;
} else {
dev_err(&client->dev, "DPLL is locked, dpll_lock = 0x%02x\n", dpll_lock);
return 0;
}
}
static int max96712_auto_init_deskew(struct i2c_client *client, u32 deskew_mask)
@@ -1363,6 +1413,12 @@ static int __max96712_start_stream(struct max96712 *max96712)
if (ret)
return ret;
link_freq_idx = max96712->cur_mode->link_freq_idx;
link_freq_mhz = (u32)div_s64(link_freq_items[link_freq_idx], 1000000L);
ret = max96712_dphy_dpll_predef_set(max96712->client, link_freq_mhz);
if (ret)
return ret;
if (max96712->auto_init_deskew_mask != 0) {
ret = max96712_auto_init_deskew(max96712->client,
max96712->auto_init_deskew_mask);
@@ -1370,12 +1426,6 @@ static int __max96712_start_stream(struct max96712 *max96712)
return ret;
}
link_freq_idx = max96712->cur_mode->link_freq_idx;
link_freq_mhz = (u32)div_s64(link_freq_items[link_freq_idx], 1000000L);
ret = max96712_dphy_dpll_predef_set(max96712->client, link_freq_mhz);
if (ret)
return ret;
if (max96712->frame_sync_period != 0) {
ret = max96712_frame_sync_period(max96712->client,
max96712->frame_sync_period);
@@ -1938,7 +1988,7 @@ static int max96712_probe(struct i2c_client *client,
if (ret)
goto err_free_handler;
ret = max96712_check_link_lock_state(max96712);
ret = max96712_check_local_chipid(max96712);
if (ret)
goto err_power_off;

16
drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
View File

@@ -1731,15 +1731,31 @@ static void samsung_mipi_cphy_power_on(struct samsung_mipi_dcphy *samsung)
reset_control_deassert(samsung->m_phy_rst);
}
static struct v4l2_subdev *get_remote_sensor(struct v4l2_subdev *sd);
static int samsung_mipi_dcphy_power_on(struct phy *phy)
{
struct samsung_mipi_dcphy *samsung = phy_get_drvdata(phy);
enum phy_mode mode = phy_get_mode(phy);
int on = 0;
struct v4l2_subdev *sensor_sd = NULL;
pm_runtime_get_sync(samsung->dev);
reset_control_assert(samsung->apb_rst);
udelay(1);
reset_control_deassert(samsung->apb_rst);
if (atomic_read(&samsung->stream_cnt)) {
sensor_sd = get_remote_sensor(&samsung->dphy_dev[0]->sd);
samsung->stream_off(samsung->dphy_dev[0], &samsung->dphy_dev[0]->sd);
if (sensor_sd)
v4l2_subdev_call(sensor_sd, core, ioctl,
RKMODULE_SET_QUICK_STREAM, &on);
samsung->stream_on(samsung->dphy_dev[0], &samsung->dphy_dev[0]->sd);
on = 1;
if (sensor_sd)
v4l2_subdev_call(sensor_sd, core, ioctl,
RKMODULE_SET_QUICK_STREAM, &on);
}
switch (mode) {
case PHY_MODE_MIPI_DPHY:

43
drivers/pwm/pwm-rockchip.c
View File

@@ -40,6 +40,14 @@
#define PWM_OUTPUT_CENTER (1 << 5)
#define PWM_LOCK_EN (1 << 6)
#define PWM_LP_DISABLE (0 << 8)
#define PWM_CLK_SEL_SHIFT 9
#define PWM_CLK_SEL_MASK (1 << PWM_CLK_SEL_SHIFT)
#define PWM_SEL_NO_SCALED_CLOCK (0 << PWM_CLK_SEL_SHIFT)
#define PWM_SEL_SCALED_CLOCK (1 << PWM_CLK_SEL_SHIFT)
#define PWM_PRESCELE_SHIFT 12
#define PWM_PRESCALE_MASK (0x3 << PWM_PRESCELE_SHIFT)
#define PWM_SCALE_SHIFT 16
#define PWM_SCALE_MASK (0xff << PWM_SCALE_SHIFT)
#define PWM_ONESHOT_COUNT_SHIFT 24
#define PWM_ONESHOT_COUNT_MASK (0xff << PWM_ONESHOT_COUNT_SHIFT)
@@ -96,6 +104,7 @@ static int rockchip_pwm_get_state(struct pwm_chip *chip,
u32 enable_conf = pc->data->enable_conf;
u64 tmp;
u32 val;
u32 dclk_div;
int ret;
if (!pc->oneshot_en) {
@@ -104,12 +113,14 @@ static int rockchip_pwm_get_state(struct pwm_chip *chip,
return 0;
}
dclk_div = pc->oneshot_en ? 2 : 1;
tmp = readl_relaxed(pc->base + pc->data->regs.period);
tmp *= pc->data->prescaler * NSEC_PER_SEC;
tmp *= dclk_div * pc->data->prescaler * NSEC_PER_SEC;
state->period = DIV_ROUND_CLOSEST_ULL(tmp, pc->clk_rate);
tmp = readl_relaxed(pc->base + pc->data->regs.duty);
tmp *= pc->data->prescaler * NSEC_PER_SEC;
tmp *= dclk_div * pc->data->prescaler * NSEC_PER_SEC;
state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, pc->clk_rate);
val = readl_relaxed(pc->base + pc->data->regs.ctrl);
@@ -164,6 +175,12 @@ static void rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
unsigned long flags;
u64 div;
u32 ctrl;
u8 dclk_div = 1;
#ifdef CONFIG_PWM_ROCKCHIP_ONESHOT
if (state->oneshot_count > 0 && state->oneshot_count <= PWM_ONESHOT_COUNT_MAX)
dclk_div = 2;
#endif
/*
* Since period and duty cycle registers have a width of 32
@@ -171,11 +188,10 @@ static void rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
* default prescaler value for all practical clock rate values.
*/
div = (u64)pc->clk_rate * state->period;
period = DIV_ROUND_CLOSEST_ULL(div,
pc->data->prescaler * NSEC_PER_SEC);
period = DIV_ROUND_CLOSEST_ULL(div, dclk_div * pc->data->prescaler * NSEC_PER_SEC);
div = (u64)pc->clk_rate * state->duty_cycle;
duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC);
duty = DIV_ROUND_CLOSEST_ULL(div, dclk_div * pc->data->prescaler * NSEC_PER_SEC);
local_irq_save(flags);
/*
@@ -194,6 +210,19 @@ static void rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
if (state->oneshot_count > 0 && state->oneshot_count <= PWM_ONESHOT_COUNT_MAX) {
u32 int_ctrl;
/*
* This is a workaround, an uncertain waveform will be
* generated after oneshot ends. It is needed to enable
* the dclk scale function to resolve it. It doesn't
* matter what the scale factor is, just make sure the
* scale function is turned on, for which we set scale
* factor to 2.
*/
ctrl &= ~PWM_SCALE_MASK;
ctrl |= (dclk_div / 2) << PWM_SCALE_SHIFT;
ctrl &= ~PWM_CLK_SEL_MASK;
ctrl |= PWM_SEL_SCALED_CLOCK;
pc->oneshot_en = true;
ctrl &= ~PWM_MODE_MASK;
ctrl |= PWM_ONESHOT;
@@ -207,6 +236,10 @@ static void rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
} else {
u32 int_ctrl;
ctrl &= ~PWM_SCALE_MASK;
ctrl &= ~PWM_CLK_SEL_MASK;
ctrl |= PWM_SEL_NO_SCALED_CLOCK;
if (state->oneshot_count)
dev_err(chip->dev, "Oneshot_count must be between 1 and 256.\n");

2
drivers/rknpu/rknpu_drv.c
View File

@@ -881,7 +881,7 @@ static int rknpu_power_off(struct rknpu_device *rknpu_dev)
#ifndef FPGA_PLATFORM
static struct monitor_dev_profile npu_mdevp = {
.type = MONITOR_TPYE_DEV,
.type = MONITOR_TYPE_DEV,
.low_temp_adjust = rockchip_monitor_dev_low_temp_adjust,
.high_temp_adjust = rockchip_monitor_dev_high_temp_adjust,
#if KERNEL_VERSION(5, 10, 0) <= LINUX_VERSION_CODE

16
drivers/soc/rockchip/rockchip_system_monitor.c
View File

@@ -708,7 +708,7 @@ static int monitor_device_parse_status_config(struct device_node *np,
&info->video_4k_freq);
ret &= of_property_read_u32(np, "rockchip,reboot-freq",
&info->reboot_freq);
if (info->devp->type == MONITOR_TPYE_CPU) {
if (info->devp->type == MONITOR_TYPE_CPU) {
if (!info->reboot_freq) {
info->reboot_freq = CPU_REBOOT_FREQ;
ret = 0;
@@ -960,7 +960,7 @@ int rockchip_monitor_suspend_low_temp_adjust(int cpu)
struct monitor_dev_info *info = NULL, *tmp;
list_for_each_entry(tmp, &monitor_dev_list, node) {
if (tmp->devp->type != MONITOR_TPYE_CPU)
if (tmp->devp->type != MONITOR_TYPE_CPU)
continue;
if (cpumask_test_cpu(cpu, &tmp->devp->allowed_cpus)) {
info = tmp;
@@ -1103,7 +1103,7 @@ rockchip_system_monitor_freq_qos_requset(struct monitor_dev_info *info)
else if (info->is_high_temp && info->high_limit)
max_default_value = info->high_limit / 1000;
if (info->devp->type == MONITOR_TPYE_CPU) {
if (info->devp->type == MONITOR_TYPE_CPU) {
policy = (struct cpufreq_policy *)info->devp->data;
ret = freq_qos_add_request(&policy->constraints,
&info->max_temp_freq_req,
@@ -1135,7 +1135,7 @@ rockchip_system_monitor_freq_qos_requset(struct monitor_dev_info *info)
freq_qos_remove_request(&info->min_sta_freq_req);
return ret;
}
} else if (info->devp->type == MONITOR_TPYE_DEV) {
} else if (info->devp->type == MONITOR_TYPE_DEV) {
devfreq = (struct devfreq *)info->devp->data;
ret = dev_pm_qos_add_request(devfreq->dev.parent,
&info->dev_max_freq_req,
@@ -1320,7 +1320,7 @@ int rockchip_monitor_check_rate_volt(struct monitor_dev_info *info)
if (opp_info && opp_info->data && opp_info->data->set_read_margin) {
is_set_rm = true;
if (info->devp->type == MONITOR_TPYE_DEV) {
if (info->devp->type == MONITOR_TYPE_DEV) {
if (!pm_runtime_active(dev)) {
is_set_rm = false;
if (opp_info->scmi_clk)
@@ -1458,7 +1458,7 @@ void rockchip_system_monitor_unregister(struct monitor_dev_info *info)
list_del(&info->node);
up_write(&mdev_list_sem);
if (info->devp->type == MONITOR_TPYE_CPU) {
if (info->devp->type == MONITOR_TYPE_CPU) {
if (freq_qos_request_active(&info->max_temp_freq_req))
freq_qos_remove_request(&info->max_temp_freq_req);
if (freq_qos_request_active(&info->min_sta_freq_req))
@@ -1690,7 +1690,7 @@ static void rockchip_system_status_limit_freq(unsigned long status)
down_read(&mdev_list_sem);
list_for_each_entry(info, &monitor_dev_list, node) {
if (info->devp->type == MONITOR_TPYE_CPU)
if (info->devp->type == MONITOR_TYPE_CPU)
rockchip_system_status_cpu_limit_freq(info, status);
}
up_read(&mdev_list_sem);
@@ -1730,7 +1730,7 @@ static int rockchip_system_monitor_set_cpu_uevent_suppress(bool is_suppress)
struct cpufreq_policy *policy;
list_for_each_entry(info, &monitor_dev_list, node) {
if (info->devp->type != MONITOR_TPYE_CPU)
if (info->devp->type != MONITOR_TYPE_CPU)
continue;
policy = (struct cpufreq_policy *)info->devp->data;
if (!policy || !policy->cdev)

2
drivers/soc/rockchip/rockchip_thunderboot_service.c
View File

@@ -97,7 +97,6 @@ static void do_mcu_done(struct rk_tb_serv *serv)
return;
}
atomic_set(&mcu_done, 1);
list_for_each_entry_safe(client, client_s, &clients_list, node) {
spin_unlock(&lock);
if (client->cb)
@@ -105,6 +104,7 @@ static void do_mcu_done(struct rk_tb_serv *serv)
spin_lock(&lock);
list_del(&client->node);
}
atomic_set(&mcu_done, 1);
spin_unlock(&lock);
}
}

2
drivers/video/rockchip/mpp/mpp_rkvdec2.c
View File

@@ -813,7 +813,7 @@ static struct devfreq_governor devfreq_vdec2_ondemand = {
};
static struct monitor_dev_profile vdec2_mdevp = {
.type = MONITOR_TPYE_DEV,
.type = MONITOR_TYPE_DEV,
.low_temp_adjust = rockchip_monitor_dev_low_temp_adjust,
.high_temp_adjust = rockchip_monitor_dev_high_temp_adjust,
};

2
drivers/video/rockchip/mpp/mpp_rkvenc.c
View File

@@ -951,7 +951,7 @@ static struct devfreq_governor devfreq_venc_ondemand = {
};
static struct monitor_dev_profile enc_mdevp = {
.type = MONITOR_TPYE_DEV,
.type = MONITOR_TYPE_DEV,
.low_temp_adjust = rockchip_monitor_dev_low_temp_adjust,
.high_temp_adjust = rockchip_monitor_dev_high_temp_adjust,
};

2
drivers/video/rockchip/mpp/mpp_rkvenc2.c
View File

@@ -1712,7 +1712,7 @@ static const struct of_device_id rockchip_rkvenc_of_match[] = {
};
static struct monitor_dev_profile venc_mdevp = {
.type = MONITOR_TPYE_DEV,
.type = MONITOR_TYPE_DEV,
.update_volt = rockchip_monitor_check_rate_volt,
};

4
include/soc/rockchip/rockchip_system_monitor.h
View File

@@ -11,8 +11,8 @@
#include <linux/regulator/consumer.h>
enum monitor_dev_type {
MONITOR_TPYE_CPU = 0, /* CPU */
MONITOR_TPYE_DEV, /* GPU, NPU, DMC, and so on */
MONITOR_TYPE_CPU = 0, /* CPU */
MONITOR_TYPE_DEV, /* GPU, NPU, DMC, and so on */
};
enum system_monitor_event_type {