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clk: rockchip: rk3128: fix incorrect configuration

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1. The first parent name of sclk_cif_out_src is wrong, it is
"sclk_cif_src".
2. The MUX configuration for sclk_cif_out_src is wrong, it should
be muxdiv_offset=29, mux_shift=2, mux_width=1.

Change-Id: I36a0ec0791afdef398d37ac8b92b7831619fb01b
Signed-off-by: Liang Chen <cl@rock-chips.com>
This commit is contained in:
Liang Chen
2017-11-22 16:10:48 +08:00
committed by Tao Huang
parent dfc5ba5499
commit d79c36b2fd
1 changed files with 2 additions and 2 deletions
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4
drivers/clk/rockchip/clk-rk3128.c
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@@ -147,7 +147,7 @@ PNAME(mux_pll_src_3plls_p) = { "cpll", "gpll", "gpll_div2" };
PNAME(mux_aclk_peri_src_p) = { "gpll_peri", "cpll_peri", "gpll_div2_peri", "gpll_div3_peri" };
PNAME(mux_mmc_src_p) = { "cpll", "gpll", "gpll_div2", "xin24m" };
PNAME(mux_clk_cif_out_src_p) = { "clk_cif_src", "xin24m" };
PNAME(mux_clk_cif_out_src_p) = { "sclk_cif_src", "xin24m" };
PNAME(mux_sclk_vop_src_p) = { "cpll", "gpll", "gpll_div2", "gpll_div3" };
PNAME(mux_i2s0_p) = { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" };
@@ -356,7 +356,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
RK2928_CLKSEL_CON(29), 0, 2, MFLAGS,
RK2928_CLKGATE_CON(3), 7, GFLAGS),
MUX(SCLK_CIF_OUT_SRC, "sclk_cif_out_src", mux_clk_cif_out_src_p, 0,
RK2928_CLKSEL_CON(13), 14, 2, MFLAGS),
RK2928_CLKSEL_CON(29), 7, 1, MFLAGS),
DIV(SCLK_CIF_OUT, "sclk_cif_out", "sclk_cif_out_src", 0,
RK2928_CLKSEL_CON(29), 2, 5, DFLAGS),