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media: rockchip: isp: add isp35

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Change-Id: I1f254e64426307983d3a223c761ea9480772b32c
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
This commit is contained in:
Cai YiWei
2024-12-06 10:25:31 +08:00
committed by Tao Huang
parent bd86f00ac7
commit d80d956f28
43 changed files with 13507 additions and 361 deletions
Download Patch File Download Diff File Expand all files Collapse all files

30
drivers/media/platform/rockchip/isp/Kconfig
View File

@@ -40,16 +40,6 @@ config VIDEO_ROCKCHIP_ISP_VERSION_V32
depends on CPU_RV1106 || CPU_RK3562
default y
config VIDEO_ROCKCHIP_ISP_VERSION_V39
bool "isp39 for rk3576"
depends on CPU_RK3576
default y
config VIDEO_ROCKCHIP_ISP_VERSION_V39_DBG
bool "isp39 params debug for rk3576"
depends on VIDEO_ROCKCHIP_ISP_VERSION_V39
default n
config VIDEO_ROCKCHIP_ISP_VERSION_V33
bool "isp33 for rv1103b"
depends on CPU_RV1103B
@@ -60,6 +50,26 @@ config VIDEO_ROCKCHIP_ISP_VERSION_V33_DBG
depends on VIDEO_ROCKCHIP_ISP_VERSION_V33
default n
config VIDEO_ROCKCHIP_ISP_VERSION_V35
bool "isp35 for rv1126b"
depends on CPU_RV1126B
default y
config VIDEO_ROCKCHIP_ISP_VERSION_V35_DBG
bool "isp35 params debug for rv1126b"
depends on VIDEO_ROCKCHIP_ISP_VERSION_V35
default n
config VIDEO_ROCKCHIP_ISP_VERSION_V39
bool "isp39 for rk3576"
depends on CPU_RK3576
default y
config VIDEO_ROCKCHIP_ISP_VERSION_V39_DBG
bool "isp39 params debug for rk3576"
depends on VIDEO_ROCKCHIP_ISP_VERSION_V39
default n
config VIDEO_ROCKCHIP_THUNDER_BOOT_ISP
bool "Rockchip Image Signal Processing Thunderboot helper"
depends on ROCKCHIP_THUNDER_BOOT

8
drivers/media/platform/rockchip/isp/Makefile
View File

@@ -57,6 +57,14 @@ video_rkisp-$(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V33) += \
isp_stats_v33.o \
isp_rockit.o
video_rkisp-$(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V35) += \
capture_v35.o \
isp_params_v35.o \
isp_stats_v35.o \
isp_pdaf.o \
isp_sditf.o \
isp_rockit.o
video_rkisp-$(CONFIG_ROCKCHIP_DVBM) += \
isp_dvbm.o

54
drivers/media/platform/rockchip/isp/capture.c
View File

@@ -863,10 +863,8 @@ static int rkisp_set_fmt(struct rkisp_stream *stream,
t = &dev->cap_dev.stream[i];
if (t->out_isp_fmt.fmt_type != FMT_YUV || !t->streaming)
continue;
/* isp v32 v33 mp wrap can't use for iqtool */
if (i == RKISP_STREAM_MP &&
(dev->isp_ver == ISP_V32 || dev->isp_ver == ISP_V33) &&
dev->cap_dev.wrap_line)
/* mp wrap can't use for iqtool */
if (i == RKISP_STREAM_MP && dev->cap_dev.wrap_line)
continue;
if (t->out_fmt.plane_fmt[0].sizeimage > imagsize) {
imagsize = t->out_fmt.plane_fmt[0].sizeimage;
@@ -896,10 +894,20 @@ static int rkisp_set_fmt(struct rkisp_stream *stream,
plane_fmt = pixm->plane_fmt + i;
w = (fmt->fmt_type == FMT_FBC) ?
ALIGN(pixm->width, 16) : pixm->width;
h = (fmt->fmt_type == FMT_FBC) ?
ALIGN(pixm->height, 16) : pixm->height;
switch (fmt->fmt_type) {
case FMT_FBC:
w = ALIGN(pixm->width, 16);
h = ALIGN(pixm->height, 16);
break;
case FMT_TILE:
w = (pixm->width + 3) / 4;
h = pixm->height / 4;
break;
default:
w = pixm->width;
h = pixm->height;
break;
}
if (stream->id == RKISP_STREAM_LDC)
w = ALIGN(pixm->width, 32);
/* mainpath for warp default */
@@ -921,6 +929,8 @@ static int rkisp_set_fmt(struct rkisp_stream *stream,
stream->id != RKISP_STREAM_SP)
/* compact mode need bytesperline 4byte align */
bytesperline = ALIGN(width * fmt->bpp[i] / 8, 256);
else if (fmt->fmt_type == FMT_TILE)
bytesperline = width * fmt->bpp[i];
else
bytesperline = width * DIV_ROUND_UP(fmt->bpp[i], 8);
@@ -1297,8 +1307,7 @@ static int rkisp_get_wrap_line(struct rkisp_stream *stream, struct rkisp_wrap_in
{
struct rkisp_device *dev = stream->ispdev;
if (stream->id != RKISP_STREAM_MP &&
dev->isp_ver != ISP_V32 && dev->isp_ver != ISP_V33)
if (!stream->ops->set_wrap)
return -EINVAL;
arg->width = dev->cap_dev.wrap_width;
@@ -1382,10 +1391,8 @@ static int rkisp_set_iqtool_connect_id(struct rkisp_stream *stream, int stream_i
goto err;
}
if ((dev->isp_ver == ISP_V32 || dev->isp_ver == ISP_V33) &&
(stream_id == RKISP_STREAM_MP) &&
dev->cap_dev.wrap_line) {
v4l2_err(&dev->v4l2_dev, "isp v32 v33 mp wrap can't use for iqtool");
if (stream_id == RKISP_STREAM_MP && dev->cap_dev.wrap_line) {
v4l2_err(&dev->v4l2_dev, "mp wrap can't use for iqtool");
goto err;
}
@@ -1579,6 +1586,16 @@ static int rkisp_enum_fmt_vid_cap_mplane(struct file *file, void *priv,
"Shield pix data 16-bit",
sizeof(f->description));
break;
case V4L2_PIX_FMT_TILE420:
strscpy(f->description,
"Rockchip yuv420 tile",
sizeof(f->description));
break;
case V4L2_PIX_FMT_TILE422:
strscpy(f->description,
"Rockchip yuv422 tile",
sizeof(f->description));
break;
default:
break;
}
@@ -1807,9 +1824,6 @@ static void rkisp_stream_fast(struct work_struct *work)
struct v4l2_subdev *sd = ispdev->active_sensor->sd;
int ret;
if (ispdev->isp_ver != ISP_V32 && ispdev->isp_ver != ISP_V33)
return;
mutex_lock(&ispdev->hw_dev->dev_lock);
rkisp_chk_tb_over(ispdev);
mutex_unlock(&ispdev->hw_dev->dev_lock);
@@ -1954,6 +1968,8 @@ int rkisp_register_stream_vdevs(struct rkisp_device *dev)
ret = rkisp_register_stream_v39(dev);
} else if (dev->isp_ver == ISP_V33) {
ret = rkisp_register_stream_v33(dev);
} else if (dev->isp_ver == ISP_V35) {
ret = rkisp_register_stream_v35(dev);
}
INIT_WORK(&cap_dev->fast_work, rkisp_stream_fast);
@@ -1976,6 +1992,8 @@ void rkisp_unregister_stream_vdevs(struct rkisp_device *dev)
rkisp_unregister_stream_v39(dev);
else if (dev->isp_ver == ISP_V33)
rkisp_unregister_stream_v33(dev);
else if (dev->isp_ver == ISP_V35)
rkisp_unregister_stream_v35(dev);
}
void rkisp_mi_isr(u32 mis_val, struct rkisp_device *dev)
@@ -1994,6 +2012,8 @@ void rkisp_mi_isr(u32 mis_val, struct rkisp_device *dev)
rkisp_mi_v39_isr(mis_val, dev);
else if (dev->isp_ver == ISP_V33)
rkisp_mi_v33_isr(mis_val, dev);
else if (dev->isp_ver == ISP_V35)
rkisp_mi_v35_isr(mis_val, dev);
}
void rkisp_mipi_v3x_isr(unsigned int phy, unsigned int packet,

1658
drivers/media/platform/rockchip/isp/capture_v35.c Normal file
View File

File diff suppressed because it is too large Load Diff

14
drivers/media/platform/rockchip/isp/capture_v3x.h
View File

@@ -40,7 +40,19 @@ static inline void rkisp_unregister_stream_v33(struct rkisp_device *dev) {}
static inline void rkisp_mi_v33_isr(u32 mis_val, struct rkisp_device *dev) {}
#endif
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V32) || IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V33)
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V35)
int rkisp_register_stream_v35(struct rkisp_device *dev);
void rkisp_unregister_stream_v35(struct rkisp_device *dev);
void rkisp_mi_v35_isr(u32 mis_val, struct rkisp_device *dev);
#else
static inline int rkisp_register_stream_v35(struct rkisp_device *dev) { return -EINVAL; }
static inline void rkisp_unregister_stream_v35(struct rkisp_device *dev) {}
static inline void rkisp_mi_v35_isr(u32 mis_val, struct rkisp_device *dev) {}
#endif
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V32) || \
IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V33) || \
IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V35)
void rkisp_rockit_buf_state_clear(struct rkisp_stream *stream);
int rkisp_rockit_buf_free(struct rkisp_stream *stream);
void rkisp_rockit_dev_init(struct rkisp_device *dev);

2
drivers/media/platform/rockchip/isp/common.h
View File

@@ -79,6 +79,7 @@ enum rkisp_isp_ver {
ISP_V32_L = 0x80,
ISP_V33 = 0x90,
ISP_V39 = 0xa0,
ISP_V35 = 0xb0,
};
enum rkisp_sd_type {
@@ -105,6 +106,7 @@ enum rkisp_fmt_pix_type {
FMT_EBD,
FMT_SPD,
FMT_FBC,
FMT_TILE,
FMT_MAX
};

10
drivers/media/platform/rockchip/isp/csi.c
View File

@@ -418,7 +418,7 @@ int rkisp_expander_config(struct rkisp_device *dev,
u32 i, val, num, d0, d1, drop_bit = 0;
u32 output_bit, input_bit, max;
if (dev->isp_ver != ISP_V39)
if (dev->isp_ver != ISP_V39 && dev->isp_ver != ISP_V35)
return 0;
if (!on) {
@@ -618,7 +618,8 @@ int rkisp_csi_config_patch(struct rkisp_device *dev, bool is_pre_cfg)
RKISP_VICAP_CMD_INIT_BUF, &init_buf);
}
if (dev->is_pre_on && !is_pre_cfg) {
if (dev->isp_ver == ISP_V33 && dev->cap_dev.wrap_line) {
if (dev->cap_dev.wrap_line &&
(dev->isp_ver == ISP_V33 || dev->isp_ver == ISP_V35)) {
val = ISP33_SW_ISP2ENC_PATH_EN | ISP33_PP_ENC_PIPE_EN;
rkisp_unite_set_bits(dev, CTRL_SWS_CFG, 0, val, false);
}
@@ -670,8 +671,9 @@ int rkisp_csi_config_patch(struct rkisp_device *dev, bool is_pre_cfg)
val = 0;
if (IS_HDR_RDBK(dev->hdr.op_mode))
val |= SW_MPIP_DROP_FRM_DIS;
if (dev->isp_ver == ISP_V33 && dev->cap_dev.wrap_line) {
val |= ISP33_SW_ISP2ENC_PATH_EN;
if (dev->cap_dev.wrap_line) {
if (dev->isp_ver == ISP_V33 || dev->isp_ver == ISP_V35)
val |= ISP33_SW_ISP2ENC_PATH_EN;
if (IS_HDR_RDBK(dev->hdr.op_mode))
val |= ISP33_PP_ENC_PIPE_EN;
}

11
drivers/media/platform/rockchip/isp/dev.c
View File

@@ -1,5 +1,5 @@
/*
* Rockchip isp1 driver
* Rockchip isp driver
*
* Copyright (C) 2017 Rockchip Electronics Co., Ltd.
*
@@ -308,7 +308,8 @@ static int rkisp_pipeline_open(struct rkisp_pipeline *p,
rkisp_vicap_buf[dev->dev_id] = RKISP_VICAP_BUF_CNT_MAX;
dev->vicap_buf_cnt = rkisp_vicap_buf[dev->dev_id];
dev->is_m_online = rkisp_m_online[dev->dev_id];
if (hw->isp_ver != ISP_V33 || hw->is_single) {
if (hw->is_single ||
(hw->isp_ver != ISP_V33 && hw->isp_ver != ISP_V35)) {
dev->is_m_online = false;
rkisp_m_online[dev->dev_id] = false;
}
@@ -324,7 +325,7 @@ static int rkisp_pipeline_open(struct rkisp_pipeline *p,
v4l2_subdev_call(dev->active_sensor->sd, core,
ioctl, RKISP_VICAP_CMD_MULTI_ONLINE, &ret);
}
if (hw->isp_ver == ISP_V33) {
if (hw->isp_ver == ISP_V33 || hw->isp_ver == ISP_V35) {
if (dev->unite_div != ISP_UNITE_DIV1)
rkisp_hdr_wrap_line[dev->dev_id] = 0;
dev->hdr_wrap_line = rkisp_hdr_wrap_line[dev->dev_id];
@@ -1276,7 +1277,7 @@ static int rkisp_pm_resume(struct device *dev)
{
struct rkisp_device *isp_dev = dev_get_drvdata(dev);
if (isp_dev->isp_ver == ISP_V33)
if (isp_dev->isp_ver == ISP_V33 || isp_dev->isp_ver == ISP_V35)
return rkisp_resume(dev);
return 0;
}
@@ -1285,7 +1286,7 @@ static void rkisp_pm_complete(struct device *dev)
{
struct rkisp_device *isp_dev = dev_get_drvdata(dev);
if (isp_dev->isp_ver == ISP_V33)
if (isp_dev->isp_ver == ISP_V33 || isp_dev->isp_ver == ISP_V35)
return;
rkisp_resume(dev);
}

2
drivers/media/platform/rockchip/isp/dev.h
View File

@@ -229,7 +229,7 @@ struct rkisp_device {
struct rkisp_csi_device csi_dev;
struct rkisp_bridge_device br_dev;
struct rkisp_luma_vdev luma_vdev;
struct rkisp_pdaf_vdev pdaf_vdev;
struct rkisp_pdaf_vdev *pdaf_vdev;
struct rkisp_procfs procfs;
struct rkisp_pipeline pipe;
enum rkisp_isp_ver isp_ver;

263
drivers/media/platform/rockchip/isp/hw.c
View File

@@ -79,7 +79,7 @@ static void default_sw_reg_flag(struct rkisp_device *dev)
ISP_RAWHIST_BIG3_BASE, ISP_YUVAE_CTRL, ISP_RAWAF_CTRL,
ISP21_RAWAWB_CTRL,
};
u32 v30_reg[] = {
u32 v3x_reg[] = {
ISP3X_VI_ISP_PATH, ISP3X_IMG_EFF_CTRL, ISP3X_CMSK_CTRL0,
ISP3X_CCM_CTRL, ISP3X_CPROC_CTRL, ISP3X_DUAL_CROP_CTRL,
ISP3X_GAMMA_OUT_CTRL, ISP3X_SELF_RESIZE_CTRL, ISP3X_MAIN_RESIZE_CTRL,
@@ -93,56 +93,12 @@ static void default_sw_reg_flag(struct rkisp_device *dev)
ISP3X_RAWAE_BIG2_BASE, ISP3X_RAWAE_BIG3_BASE, ISP3X_RAWHIST_LITE_CTRL,
ISP3X_RAWHIST_BIG1_BASE, ISP3X_RAWHIST_BIG2_BASE, ISP3X_RAWHIST_BIG3_BASE,
ISP3X_RAWAF_CTRL, ISP3X_RAWAWB_CTRL,
};
u32 v32_reg[] = {
ISP3X_VI_ISP_PATH, ISP3X_IMG_EFF_CTRL, ISP3X_CMSK_CTRL0,
ISP3X_CCM_CTRL, ISP3X_CPROC_CTRL, ISP3X_DUAL_CROP_CTRL,
ISP3X_GAMMA_OUT_CTRL, ISP3X_SELF_RESIZE_CTRL, ISP3X_MAIN_RESIZE_CTRL,
ISP32_BP_RESIZE_BASE, ISP3X_MI_BP_WR_CTRL, ISP32_MI_MPDS_WR_CTRL,
ISP32_MI_BPDS_WR_CTRL, ISP32_MI_WR_WRAP_CTRL,
ISP3X_LSC_CTRL, ISP3X_DEBAYER_CONTROL, ISP3X_CAC_CTRL,
ISP3X_YNR_GLOBAL_CTRL, ISP3X_CNR_CTRL, ISP3X_SHARP_EN,
ISP3X_BAY3D_CTRL, ISP3X_GIC_CONTROL, ISP3X_BLS_CTRL,
ISP3X_DPCC0_MODE, ISP3X_DPCC1_MODE, ISP3X_DPCC2_MODE,
ISP3X_HDRMGE_CTRL, ISP3X_DRC_CTRL0, ISP3X_BAYNR_CTRL,
ISP3X_LDCH_STS, ISP3X_DHAZ_CTRL, ISP3X_3DLUT_CTRL,
ISP3X_GAIN_CTRL, ISP3X_RAWAE_LITE_CTRL, ISP3X_RAWAE_BIG1_BASE,
ISP3X_RAWAE_BIG2_BASE, ISP3X_RAWAE_BIG3_BASE, ISP3X_RAWHIST_LITE_CTRL,
ISP3X_RAWHIST_BIG1_BASE, ISP3X_RAWHIST_BIG2_BASE, ISP3X_RAWHIST_BIG3_BASE,
ISP3X_RAWAF_CTRL, ISP3X_RAWAWB_CTRL,
};
u32 v39_reg[] = {
ISP3X_VI_ISP_PATH, ISP3X_IMG_EFF_CTRL, ISP3X_CMSK_CTRL0,
ISP3X_CCM_CTRL, ISP3X_CPROC_CTRL, ISP3X_DUAL_CROP_CTRL,
ISP3X_GAMMA_OUT_CTRL, ISP39_MAIN_SCALE_CTRL, ISP32_SELF_SCALE_CTRL,
ISP32_MI_BPDS_WR_CTRL, ISP32_MI_WR_WRAP_CTRL, ISP3X_MI_WR_CTRL,
ISP39_LDCV_CTRL, ISP39_YUVME_CTRL, ISP39_RGBIR_CTRL,
ISP39_EXPD_CTRL, ISP39_W3A_CTRL0, ISP39_W3A_CTRL1,
ISP3X_LSC_CTRL, ISP3X_DEBAYER_CONTROL, ISP3X_CAC_CTRL,
ISP3X_YNR_GLOBAL_CTRL, ISP3X_CNR_CTRL, ISP3X_SHARP_EN,
ISP3X_BAY3D_CTRL, ISP3X_GIC_CONTROL, ISP3X_BLS_CTRL,
ISP3X_DPCC0_MODE, ISP3X_DPCC1_MODE, ISP3X_DPCC2_MODE,
ISP3X_HDRMGE_CTRL, ISP3X_DRC_CTRL0, ISP3X_BAYNR_CTRL,
ISP3X_LDCH_STS, ISP3X_DHAZ_CTRL, ISP3X_3DLUT_CTRL,
ISP3X_GAIN_CTRL, ISP3X_RAWAE_LITE_CTRL, ISP3X_RAWAE_BIG1_BASE,
ISP3X_RAWAE_BIG2_BASE, ISP3X_RAWAE_BIG3_BASE, ISP3X_RAWHIST_LITE_CTRL,
ISP3X_RAWHIST_BIG1_BASE, ISP3X_RAWHIST_BIG2_BASE, ISP3X_RAWHIST_BIG3_BASE,
ISP3X_RAWAF_CTRL, ISP3X_RAWAWB_CTRL,
};
u32 v33_reg[] = {
ISP3X_VI_ISP_PATH, ISP3X_IMG_EFF_CTRL, ISP3X_CMSK_CTRL0,
ISP3X_CCM_CTRL, ISP3X_CPROC_CTRL, ISP3X_DUAL_CROP_CTRL,
ISP3X_GAMMA_OUT_CTRL, ISP39_MAIN_SCALE_CTRL, ISP33_BP_SCALE_CTRL,
ISP32_SELF_SCALE_CTRL, ISP3X_MI_WR_CTRL, ISP3X_MI_BP_WR_CTRL,
ISP32_MI_WR_WRAP_CTRL, ISP3X_LSC_CTRL, ISP3X_DEBAYER_CONTROL,
ISP3X_CAC_CTRL, ISP3X_YNR_GLOBAL_CTRL, ISP3X_CNR_CTRL,
ISP3X_SHARP_EN, ISP33_BAY3D_CTRL0, ISP3X_GIC_CONTROL,
ISP3X_BLS_CTRL, ISP3X_DPCC0_MODE, ISP3X_DPCC1_MODE,
ISP3X_DPCC2_MODE, ISP3X_HDRMGE_CTRL, ISP3X_DRC_CTRL0,
ISP33_ENH_CTRL, ISP3X_LDCH_STS, ISP33_HIST_CTRL,
ISP33_HSV_CTRL, ISP3X_GAIN_CTRL, ISP39_W3A_CTRL0,
ISP3X_RAWAE_LITE_CTRL, ISP3X_RAWAE_BIG1_BASE,
ISP3X_RAWHIST_LITE_CTRL, ISP3X_RAWHIST_BIG1_BASE,
ISP3X_RAWAWB_CTRL,
ISP33_BP_SCALE_CTRL, ISP33_BAY3D_CTRL0, ISP33_HIST_CTRL,
ISP35_AI_CTRL, ISP35_AIAWB_CTRL0
};
u32 i, j, *flag, *reg, size;
@@ -155,25 +111,10 @@ static void default_sw_reg_flag(struct rkisp_device *dev)
reg = v21_reg;
size = ARRAY_SIZE(v21_reg);
break;
case ISP_V30:
reg = v30_reg;
size = ARRAY_SIZE(v30_reg);
break;
case ISP_V32:
case ISP_V32_L:
reg = v32_reg;
size = ARRAY_SIZE(v32_reg);
break;
case ISP_V39:
reg = v39_reg;
size = ARRAY_SIZE(v39_reg);
break;
case ISP_V33:
reg = v33_reg;
size = ARRAY_SIZE(v33_reg);
break;
default:
return;
reg = v3x_reg;
size = ARRAY_SIZE(v3x_reg);
break;
}
for (i = 0; i < size; i++) {
@@ -453,15 +394,20 @@ void rkisp_hw_reg_restore(struct rkisp_hw_dev *dev)
for (j = 0; j < ARRAY_SIZE(self_upd_reg); j++) {
reg = reg_buf + self_upd_reg[j];
*reg &= ~ISP21_SELF_FORCE_UPD;
if (self_upd_reg[j] == ISP3X_3DLUT_BASE && *reg & ISP_3DLUT_EN) {
if (self_upd_reg[j] == ISP3X_3DLUT_BASE &&
*reg & ISP_3DLUT_EN &&
dev->isp_ver != ISP_V35) {
reg = reg_buf + ISP3X_3DLUT_UPDATE;
*reg = 1;
}
}
if (dev->isp_ver == ISP_V39) {
reg = reg_buf + ISP39_VI3A_CTRL0;
if (*reg)
*reg |= ISP39_W3A_FORCE_UPD;
if (dev->isp_ver == ISP_V35) {
reg = reg_buf + ISP3X_SWS_CFG;
*reg &= ~ISP3X_3A_DDR_WRITE_EN;
reg = reg_buf + ISP39_W3A_CTRL0;
*reg &= ~ISP39_W3A_FORCE_UPD;
reg = reg_buf + ISP35_AIAWB_CTRL0;
*reg &= ~ISP35_AIAWB_SELF_UPD;
}
reg = reg_buf + ISP_CTRL;
*reg &= ~(CIF_ISP_CTRL_ISP_ENABLE |
@@ -479,7 +425,7 @@ void rkisp_hw_reg_restore(struct rkisp_hw_dev *dev)
(j == 0x4840 || j == 0x4a80 || j == 0x4b40 || j == 0x5660) ||
(dev->isp_ver == ISP_V39 &&
(j > ISP39_DHAZ_HIST_IIR0 && j < ISP39_DHAZ_LINE_CNT)) ||
(dev->isp_ver == ISP_V33 &&
((dev->isp_ver == ISP_V33 || dev->isp_ver == ISP_V35) &&
((j > ISP33_ENH_IIR0 && j < ISP33_ENH_ERR_FLAG) ||
(j > ISP33_HIST_IIR0 && j < ISP33_HIST_STAB) ||
(j >= ISP33_SHARP_NOISE_CURVE0 && j <= ISP33_SHARP_NOISE_CURVE8))))
@@ -546,7 +492,7 @@ void rkisp_hw_reg_restore(struct rkisp_hw_dev *dev)
writel(*reg | CIF_DUAL_CROP_CFG_UPD, base + DUAL_CROP_CTRL);
reg = reg_buf + SELF_RESIZE_CTRL;
if (*reg & 0xf) {
if (dev->isp_ver == ISP_V32_L || dev->isp_ver == ISP_V39 || dev->isp_ver == ISP_V33)
if (dev->isp_ver >= ISP_V32_L)
writel(ISP32_SCALE_FORCE_UPD | ISP32_SCALE_GEN_UPD,
base + ISP32_SELF_SCALE_UPDATE);
else
@@ -554,7 +500,7 @@ void rkisp_hw_reg_restore(struct rkisp_hw_dev *dev)
}
reg = reg_buf + MAIN_RESIZE_CTRL;
if (*reg & 0xf) {
if (dev->isp_ver == ISP_V39 || dev->isp_ver == ISP_V33)
if (dev->isp_ver >= ISP_V33)
writel(ISP32_SCALE_FORCE_UPD | ISP32_SCALE_GEN_UPD,
base + ISP39_MAIN_SCALE_UPDATE);
else
@@ -594,40 +540,57 @@ void rkisp_hw_reg_restore(struct rkisp_hw_dev *dev)
val = rkisp_read_reg_cache(isp, ISP3X_CAC_BASE);
writel(val, base + ISP3X_CAC_BASE);
}
if (dev->isp_ver == ISP_V35) {
reg = reg_buf + ISP39_W3A_CTRL0;
if (*reg & ISP39_W3A_EN) {
reg = reg_buf + ISP3X_SWS_CFG;
*reg |= ISP3X_3A_DDR_WRITE_EN;
writel(*reg, base + ISP3X_SWS_CFG);
}
reg = reg_buf + ISP35_AIAWB_CTRL0;
if (*reg & ISP35_AIAWB_EN) {
*reg |= ISP35_AIAWB_SELF_UPD;
writel(*reg, base + ISP35_AIAWB_CTRL0);
}
}
}
if (dev->is_single) {
rkisp_params_cfgsram(&isp->params_vdev, false, true);
if (dev->isp_ver == ISP_V39) {
reg = reg_buf + ISP3X_ISP_CTRL1;
*reg |= ISP3X_DHAZ_FST_FRAME;
writel(*reg, dev->base_addr + ISP3X_ISP_CTRL1);
reg = reg_buf + ISP3X_BAY3D_CTRL;
if (*reg & 1)
writel(*reg | BIT(31), dev->base_addr + ISP3X_BAY3D_CTRL);
/* w3a addr will update by ISP_CFG_UPD */
reg = reg_buf + ISP39_W3A_AEBIG_ADDR_SHD;
writel(*reg, dev->base_addr + ISP39_W3A_AEBIG_ADDR);
reg = reg_buf + ISP39_W3A_AE0_ADDR_SHD;
writel(*reg, dev->base_addr + ISP39_W3A_AE0_ADDR);
reg = reg_buf + ISP39_W3A_AF_ADDR_SHD;
writel(*reg, dev->base_addr + ISP39_W3A_AF_ADDR);
reg = reg_buf + ISP39_W3A_AWB_ADDR_SHD;
writel(*reg, dev->base_addr + ISP39_W3A_AWB_ADDR);
reg = reg_buf + ISP39_W3A_PDAF_ADDR_SHD;
writel(*reg, dev->base_addr + ISP39_W3A_PDAF_ADDR);
} else if (dev->isp_ver == ISP_V33) {
reg = reg_buf + ISP33_BAY3D_CTRL0;
if (*reg & 1)
writel(*reg | BIT(31), dev->base_addr + ISP33_BAY3D_CTRL0);
/* w3a addr will update by ISP_CFG_UPD */
if (dev->isp_ver >= ISP_V33) {
if (dev->isp_ver == ISP_V39) {
reg = reg_buf + ISP3X_ISP_CTRL1;
*reg |= ISP3X_DHAZ_FST_FRAME;
writel(*reg, dev->base_addr + ISP3X_ISP_CTRL1);
reg = reg_buf + ISP3X_BAY3D_CTRL;
if (*reg & 1)
writel(*reg | BIT(31), dev->base_addr + ISP3X_BAY3D_CTRL);
} else {
reg = reg_buf + ISP33_BAY3D_CTRL0;
if (*reg & 1)
writel(*reg | BIT(31), dev->base_addr + ISP33_BAY3D_CTRL0);
}
/* V33 and V39 w3a addr will update by ISP_CFG_UPD */
reg = reg_buf + ISP39_W3A_AEBIG_ADDR_SHD;
writel(*reg, dev->base_addr + ISP39_W3A_AEBIG_ADDR);
reg = reg_buf + ISP39_W3A_AE0_ADDR_SHD;
writel(*reg, dev->base_addr + ISP39_W3A_AE0_ADDR);
reg = reg_buf + ISP39_W3A_AWB_ADDR_SHD;
writel(*reg, dev->base_addr + ISP39_W3A_AWB_ADDR);
if (dev->isp_ver != ISP_V33) {
reg = reg_buf + ISP39_W3A_AF_ADDR_SHD;
writel(*reg, dev->base_addr + ISP39_W3A_AF_ADDR);
reg = reg_buf + ISP39_W3A_PDAF_ADDR_SHD;
writel(*reg, dev->base_addr + ISP39_W3A_PDAF_ADDR);
}
if (dev->isp_ver == ISP_V35) {
reg = reg_buf + ISP39_W3A_CTRL0;
if (*reg & ISP39_W3A_EN) {
*reg |= ISP39_W3A_FORCE_UPD;
writel(*reg, dev->base_addr + ISP39_W3A_CTRL0);
}
}
}
reg = reg_buf + ISP_CTRL;
@@ -638,14 +601,14 @@ void rkisp_hw_reg_restore(struct rkisp_hw_dev *dev)
if (dev->unite == ISP_UNITE_TWO)
writel(*reg, dev->base_next_addr + ISP_CTRL);
if (dev->isp_ver == ISP_V39 || dev->isp_ver == ISP_V33) {
if (dev->isp_ver >= ISP_V33) {
reg = reg_buf + ISP39_W3A_AEBIG_ADDR;
writel(*reg, dev->base_addr + ISP39_W3A_AEBIG_ADDR);
reg = reg_buf + ISP39_W3A_AE0_ADDR;
writel(*reg, dev->base_addr + ISP39_W3A_AE0_ADDR);
reg = reg_buf + ISP39_W3A_AWB_ADDR;
writel(*reg, dev->base_addr + ISP39_W3A_AWB_ADDR);
if (dev->isp_ver == ISP_V39) {
if (dev->isp_ver != ISP_V33) {
reg = reg_buf + ISP39_W3A_AF_ADDR;
writel(*reg, dev->base_addr + ISP39_W3A_AF_ADDR);
reg = reg_buf + ISP39_W3A_PDAF_ADDR;
@@ -709,6 +672,16 @@ static const char * const rv1126_isp_clks[] = {
"hclk_isp",
};
static const char * const rv1126b_isp_clks[] = {
"clk_isp_core",
"aclk_isp",
"hclk_isp",
"clk_isp_vicap",
"clk_core_vpsl",
"aclk_vpsl",
"hclk_vpsl",
};
static const struct isp_clk_info rk3562_isp_clk_rate[] = {
{
.clk_rate = 300,
@@ -815,37 +788,7 @@ static const struct isp_clk_info rv1126_isp_clk_rate[] = {
}
};
static struct isp_irqs_data rk3562_isp_irqs[] = {
{"isp_irq", isp_irq_hdl},
{"mi_irq", mi_irq_hdl},
{"mipi_irq", mipi_irq_hdl}
};
static struct isp_irqs_data rk3568_isp_irqs[] = {
{"isp_irq", isp_irq_hdl},
{"mi_irq", mi_irq_hdl},
{"mipi_irq", mipi_irq_hdl}
};
static struct isp_irqs_data rk3576_isp_irqs[] = {
{"isp_irq", isp_irq_hdl},
{"mi_irq", mi_irq_hdl},
{"mipi_irq", mipi_irq_hdl}
};
static struct isp_irqs_data rk3588_isp_irqs[] = {
{"isp_irq", isp_irq_hdl},
{"mi_irq", mi_irq_hdl},
{"mipi_irq", mipi_irq_hdl}
};
static struct isp_irqs_data rv1106_isp_irqs[] = {
{"isp_irq", isp_irq_hdl},
{"mi_irq", mi_irq_hdl},
{"mipi_irq", mipi_irq_hdl}
};
static struct isp_irqs_data rv1126_isp_irqs[] = {
static struct isp_irqs_data isp_irqs[] = {
{"isp_irq", isp_irq_hdl},
{"mi_irq", mi_irq_hdl},
{"mipi_irq", mipi_irq_hdl}
@@ -857,8 +800,8 @@ static const struct isp_match_data rv1103b_isp_match_data = {
.isp_ver = ISP_V33,
.clk_rate_tbl = rv1106_isp_clk_rate,
.num_clk_rate_tbl = ARRAY_SIZE(rv1106_isp_clk_rate),
.irqs = rv1106_isp_irqs,
.num_irqs = ARRAY_SIZE(rv1106_isp_irqs),
.irqs = isp_irqs,
.num_irqs = ARRAY_SIZE(isp_irqs),
.unite = false,
};
@@ -868,8 +811,8 @@ static const struct isp_match_data rv1106_isp_match_data = {
.isp_ver = ISP_V32,
.clk_rate_tbl = rv1106_isp_clk_rate,
.num_clk_rate_tbl = ARRAY_SIZE(rv1106_isp_clk_rate),
.irqs = rv1106_isp_irqs,
.num_irqs = ARRAY_SIZE(rv1106_isp_irqs),
.irqs = isp_irqs,
.num_irqs = ARRAY_SIZE(isp_irqs),
.unite = false,
};
@@ -879,8 +822,19 @@ static const struct isp_match_data rv1126_isp_match_data = {
.isp_ver = ISP_V20,
.clk_rate_tbl = rv1126_isp_clk_rate,
.num_clk_rate_tbl = ARRAY_SIZE(rv1126_isp_clk_rate),
.irqs = rv1126_isp_irqs,
.num_irqs = ARRAY_SIZE(rv1126_isp_irqs),
.irqs = isp_irqs,
.num_irqs = ARRAY_SIZE(isp_irqs),
.unite = false,
};
static const struct isp_match_data rv1126b_isp_match_data = {
.clks = rv1126b_isp_clks,
.num_clks = ARRAY_SIZE(rv1126b_isp_clks),
.isp_ver = ISP_V35,
.clk_rate_tbl = rv1126_isp_clk_rate,
.num_clk_rate_tbl = ARRAY_SIZE(rv1126_isp_clk_rate),
.irqs = isp_irqs,
.num_irqs = ARRAY_SIZE(isp_irqs),
.unite = false,
};
@@ -890,8 +844,8 @@ static const struct isp_match_data rk3562_isp_match_data = {
.isp_ver = ISP_V32_L,
.clk_rate_tbl = rk3562_isp_clk_rate,
.num_clk_rate_tbl = ARRAY_SIZE(rk3562_isp_clk_rate),
.irqs = rk3562_isp_irqs,
.num_irqs = ARRAY_SIZE(rk3562_isp_irqs),
.irqs = isp_irqs,
.num_irqs = ARRAY_SIZE(isp_irqs),
.unite = false,
};
@@ -901,8 +855,8 @@ static const struct isp_match_data rk3568_isp_match_data = {
.isp_ver = ISP_V21,
.clk_rate_tbl = rk3568_isp_clk_rate,
.num_clk_rate_tbl = ARRAY_SIZE(rk3568_isp_clk_rate),
.irqs = rk3568_isp_irqs,
.num_irqs = ARRAY_SIZE(rk3568_isp_irqs),
.irqs = isp_irqs,
.num_irqs = ARRAY_SIZE(isp_irqs),
.unite = false,
};
@@ -912,8 +866,8 @@ static const struct isp_match_data rk3576_isp_match_data = {
.isp_ver = ISP_V39,
.clk_rate_tbl = rk3576_isp_clk_rate,
.num_clk_rate_tbl = ARRAY_SIZE(rk3576_isp_clk_rate),
.irqs = rk3576_isp_irqs,
.num_irqs = ARRAY_SIZE(rk3576_isp_irqs),
.irqs = isp_irqs,
.num_irqs = ARRAY_SIZE(isp_irqs),
.unite = false,
};
@@ -923,8 +877,8 @@ static const struct isp_match_data rk3588_isp_match_data = {
.isp_ver = ISP_V30,
.clk_rate_tbl = rk3588_isp_clk_rate,
.num_clk_rate_tbl = ARRAY_SIZE(rk3588_isp_clk_rate),
.irqs = rk3588_isp_irqs,
.num_irqs = ARRAY_SIZE(rk3588_isp_irqs),
.irqs = isp_irqs,
.num_irqs = ARRAY_SIZE(isp_irqs),
.unite = false,
};
@@ -934,8 +888,8 @@ static const struct isp_match_data rk3588_isp_unite_match_data = {
.isp_ver = ISP_V30,
.clk_rate_tbl = rk3588_isp_clk_rate,
.num_clk_rate_tbl = ARRAY_SIZE(rk3588_isp_clk_rate),
.irqs = rk3588_isp_irqs,
.num_irqs = ARRAY_SIZE(rk3588_isp_irqs),
.irqs = isp_irqs,
.num_irqs = ARRAY_SIZE(isp_irqs),
.unite = true,
};
@@ -984,6 +938,12 @@ static const struct of_device_id rkisp_hw_of_match[] = {
.compatible = "rockchip,rv1126-rkisp",
.data = &rv1126_isp_match_data,
},
#endif
#ifdef CONFIG_CPU_RV1126B
{
.compatible = "rockchip,rv1126b-rkisp",
.data = &rv1126b_isp_match_data,
},
#endif
{},
};
@@ -1110,6 +1070,13 @@ void rkisp_soft_reset(struct rkisp_hw_dev *dev, bool is_secure)
writel(0x02000400, dev->base_addr + ISP39_DEBAYER_G_FILTER_VSIGMA1);
writel(0x00cd0155, dev->base_addr + ISP39_DEBAYER_G_FILTER_VSIGMA2);
writel(0x00800092, dev->base_addr + ISP39_DEBAYER_G_FILTER_VSIGMA3);
} else if (dev->isp_ver == ISP_V35) {
writel(0, dev->base_addr + ISP32_BLS_ISP_OB_PREDGAIN);
writel(ISP39_ADRC_CMPS_BYP_EN, dev->base_addr + ISP3X_DRC_CTRL0);
writel(ISP39_W3A_PDAF2DDR_HOLD_DIS | ISP39_W3A_3A_HOLD_DIS | ISP35_W3A_B3DNROUT_ILG_BYPASS,
dev->base_addr + ISP39_W3A_CTRL0);
writel(0, dev->base_addr + ISP39_LDCH_OUT_SIZE);
writel(0x3801, dev->base_addr + ISP33_BAY3D_CTRL1);
}
}
@@ -1590,7 +1557,7 @@ static int __init rkisp_hw_drv_init(void)
ret = platform_driver_register(&rkisp_hw_drv);
if (!ret)
ret = platform_driver_register(&rkisp_plat_drv);
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V39)
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V39) || IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V35)
platform_driver_register(&rkisp_sditf_drv);
#endif
#if IS_BUILTIN(CONFIG_VIDEO_ROCKCHIP_ISP) && IS_BUILTIN(CONFIG_VIDEO_ROCKCHIP_ISPP)
@@ -1602,7 +1569,7 @@ static int __init rkisp_hw_drv_init(void)
static void __exit rkisp_hw_drv_exit(void)
{
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V39)
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V39) || IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V35)
platform_driver_unregister(&rkisp_sditf_drv);
#endif
platform_driver_unregister(&rkisp_plat_drv);

19
drivers/media/platform/rockchip/isp/isp_params.c
View File

@@ -16,6 +16,7 @@
#include "isp_params_v32.h"
#include "isp_params_v39.h"
#include "isp_params_v33.h"
#include "isp_params_v35.h"
#include "regs.h"
#define PARAMS_NAME DRIVER_NAME "-input-params"
@@ -102,6 +103,8 @@ static int rkisp_get_params(struct rkisp_isp_params_vdev *params_vdev, void *arg
ret = rkisp_get_params_v39(params_vdev, arg);
else if (params_vdev->dev->isp_ver == ISP_V33)
ret = rkisp_get_params_v33(params_vdev, arg);
else if (params_vdev->dev->isp_ver == ISP_V35)
ret = rkisp_get_params_v35(params_vdev, arg);
return ret;
}
@@ -117,6 +120,7 @@ static long rkisp_params_ioctl_default(struct file *file, void *fh,
break;
case RKISP_CMD_GET_PARAMS_V39:
case RKISP_CMD_GET_PARAMS_V33:
case RKISP_CMD_GET_PARAMS_V35:
ret = rkisp_get_params(params, arg);
break;
default:
@@ -248,7 +252,7 @@ static void rkisp_params_vb2_buf_queue(struct vb2_buffer *vb)
spin_unlock_irqrestore(&params_vdev->config_lock, flags);
dev_info(dev->dev, "params seq:%d for rtt\n", params->frame_id);
dev->is_first_double = false;
if (dev->isp_ver == ISP_V33) {
if (dev->isp_ver >= ISP_V33) {
dev->skip_frame = 1;
dev->is_wait_aiq = true;
}
@@ -439,6 +443,8 @@ static int rkisp_init_params_vdev(struct rkisp_isp_params_vdev *params_vdev)
ret = rkisp_init_params_vdev_v39(params_vdev);
else if (dev->isp_ver == ISP_V33)
ret = rkisp_init_params_vdev_v33(params_vdev);
else if (dev->isp_ver == ISP_V35)
ret = rkisp_init_params_vdev_v35(params_vdev);
params_vdev->vdev_fmt.fmt.meta.dataformat = V4L2_META_FMT_RK_ISP1_PARAMS;
return ret;
@@ -462,6 +468,8 @@ static void rkisp_uninit_params_vdev(struct rkisp_isp_params_vdev *params_vdev)
rkisp_uninit_params_vdev_v39(params_vdev);
else if (dev->isp_ver == ISP_V33)
rkisp_uninit_params_vdev_v33(params_vdev);
else if (dev->isp_ver == ISP_V35)
rkisp_uninit_params_vdev_v35(params_vdev);
}
void rkisp_params_cfg(struct rkisp_isp_params_vdev *params_vdev,
@@ -614,6 +622,15 @@ int rkisp_params_aiisp_start(struct rkisp_isp_params_vdev *params_vdev,
return ret;
}
int rkisp_params_get_aiawb_buffd(struct rkisp_isp_params_vdev *params_vdev, void *arg)
{
int ret = -EINVAL;
if (params_vdev->ops->get_aiawb_buffd)
ret = params_vdev->ops->get_aiawb_buffd(params_vdev, arg);
return ret;
}
int rkisp_register_params_vdev(struct rkisp_isp_params_vdev *params_vdev,
struct v4l2_device *v4l2_dev,
struct rkisp_device *dev)

4
drivers/media/platform/rockchip/isp/isp_params.h
View File

@@ -10,6 +10,7 @@
#include <linux/rk-isp32-config.h>
#include <linux/rk-isp39-config.h>
#include <linux/rk-isp33-config.h>
#include <linux/rk-isp35-config.h>
#include <linux/rk-preisp.h>
#include "common.h"
@@ -56,6 +57,7 @@ struct rkisp_isp_params_ops {
struct rkisp_bnr_buf_info *bnrbuf);
void (*aiisp_event)(struct rkisp_isp_params_vdev *params_vdev, u32 irq);
int (*aiisp_start)(struct rkisp_isp_params_vdev *params_vdev, struct rkisp_aiisp_st *st);
int (*get_aiawb_buffd)(struct rkisp_isp_params_vdev *params_vdev, void *arg);
};
/*
@@ -79,6 +81,7 @@ struct rkisp_isp_params_vdev {
struct isp32_isp_params_cfg *isp32_params;
struct isp39_isp_params_cfg *isp39_params;
struct isp33_isp_params_cfg *isp33_params;
struct isp35_isp_params_cfg *isp35_params;
};
struct v4l2_format vdev_fmt;
bool streamon;
@@ -173,4 +176,5 @@ int rkisp_params_init_bnr_buf(struct rkisp_isp_params_vdev *params_vdev,
struct rkisp_bnr_buf_info *bnrbuf);
void rkisp_params_aiisp_event(struct rkisp_isp_params_vdev *params_vdev, u32 irq);
int rkisp_params_aiisp_start(struct rkisp_isp_params_vdev *params_vdev, struct rkisp_aiisp_st *st);
int rkisp_params_get_aiawb_buffd(struct rkisp_isp_params_vdev *params_vdev, void *arg);
#endif /* _RKISP_ISP_PARAM_H */

8539
drivers/media/platform/rockchip/isp/isp_params_v35.c Normal file
View File

File diff suppressed because it is too large Load Diff

64
drivers/media/platform/rockchip/isp/isp_params_v35.h Normal file
View File

@@ -0,0 +1,64 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2025 Rockchip Electronics Co., Ltd. */
#ifndef _RKISP_ISP_PARAM_V35_H
#define _RKISP_ISP_PARAM_V35_H
#include "isp_params.h"
#define ISP35_RAWHISTBIG_ROW_NUM 15
#define ISP35_RAWHISTBIG_COLUMN_NUM 15
#define ISP35_RAWHISTBIG_WEIGHT_REG_SIZE \
(ISP35_RAWHISTBIG_ROW_NUM * ISP35_RAWHISTBIG_COLUMN_NUM)
struct rkisp_isp_params_vdev;
struct rkisp_isp_params_val_v35 {
struct rkisp_dummy_buffer buf_ldch[ISP_UNITE_MAX][ISP3X_MESH_BUF_NUM];
u32 buf_ldch_idx[ISP_UNITE_MAX];
struct rkisp_dummy_buffer buf_b3dldc[ISP_UNITE_MAX][ISP3X_MESH_BUF_NUM];
u32 buf_b3dldc_idx[ISP_UNITE_MAX];
u32 b3dldc_hsize;
u32 b3dldch_vsize;
u32 b3dldcv_vsize;
struct rkisp_dummy_buffer buf_info[RKISP_INFO2DDR_BUF_MAX];
u32 buf_info_owner;
u32 buf_info_cnt;
int buf_info_idx;
struct rkisp_dummy_buffer buf_aiawb[RKISP_BUFFER_MAX];
u32 buf_aiawb_cnt;
int buf_aiawb_idx;
struct rkisp_dummy_buffer buf_3dnr_wgt;
struct rkisp_dummy_buffer buf_3dnr_iir;
struct rkisp_dummy_buffer buf_3dnr_ds;
struct rkisp_dummy_buffer buf_gain;
u32 bay3d_iir_stride;
u32 bay3d_ds_size;
u32 bay3d_iir_size;
u32 bay3d_wgt_size;
u32 gain_size;
u32 hist_blk_num;
u32 enh_row;
u32 enh_col;
};
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V35)
int rkisp_init_params_vdev_v35(struct rkisp_isp_params_vdev *params_vdev);
void rkisp_uninit_params_vdev_v35(struct rkisp_isp_params_vdev *params_vdev);
#else
static inline int rkisp_init_params_vdev_v35(struct rkisp_isp_params_vdev *params_vdev) { return -EINVAL; }
static inline void rkisp_uninit_params_vdev_v35(struct rkisp_isp_params_vdev *params_vdev) {}
#endif
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V35_DBG)
int rkisp_get_params_v35(struct rkisp_isp_params_vdev *params_vdev, void *arg);
#else
static inline int rkisp_get_params_v35(struct rkisp_isp_params_vdev *params_vdev, void *arg)
{
pr_err("enable CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V35_DBG in kernel config\n");
return -EINVAL;
}
#endif
#endif /* _RKISP_ISP_PARAM_V35_H */

48
drivers/media/platform/rockchip/isp/isp_pdaf.c
View File

@@ -243,6 +243,8 @@ static int rkisp_pdaf_start_streaming(struct vb2_queue *vq, unsigned int count)
v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
"%s cnt:%d\n", __func__, count);
val = pdaf_vdev->fmt.plane_fmt[0].bytesperline;
if (dev->isp_ver == ISP_V35)
val = 512;
rkisp_write(dev, ISP39_W3A_CTRL1, val, false);
pdaf_vdev->streaming = true;
tasklet_enable(&pdaf_vdev->buf_done_tasklet);
@@ -303,11 +305,14 @@ static void rkisp_pdaf_buf_done_task(unsigned long arg)
void rkisp_pdaf_update_buf(struct rkisp_device *dev)
{
struct rkisp_pdaf_vdev *pdaf_vdev = &dev->pdaf_vdev;
struct rkisp_pdaf_vdev *pdaf_vdev = dev->pdaf_vdev;
struct rkisp_buffer *buf = NULL;
unsigned long flags = 0;
u32 val;
if (!pdaf_vdev)
return;
spin_lock_irqsave(&pdaf_vdev->vbq_lock, flags);
if (!pdaf_vdev->next_buf && !list_empty(&pdaf_vdev->buf_queue)) {
buf = list_first_entry(&pdaf_vdev->buf_queue,
@@ -333,11 +338,15 @@ void rkisp_pdaf_update_buf(struct rkisp_device *dev)
void rkisp_pdaf_isr(struct rkisp_device *dev)
{
struct rkisp_pdaf_vdev *pdaf_vdev = &dev->pdaf_vdev;
struct rkisp_pdaf_vdev *pdaf_vdev = dev->pdaf_vdev;
struct rkisp_buffer *buf = NULL;
unsigned long flags = 0;
u32 w3a_ris = rkisp_read(dev, ISP39_W3A_INT_STAT, true);
u32 w3a_ris;
if (!pdaf_vdev)
return;
w3a_ris = rkisp_read(dev, ISP39_W3A_INT_STAT, true);
if (w3a_ris & ISP39_W3A_INT_PDAF_OVF) {
v4l2_err(&dev->v4l2_dev, "pdaf overflow 0x%x\n", w3a_ris);
rkisp_write(dev, ISP39_W3A_INT_STAT, ISP39_W3A_INT_PDAF_OVF, true);
@@ -387,16 +396,22 @@ void rkisp_pdaf_isr(struct rkisp_device *dev)
int rkisp_register_pdaf_vdev(struct rkisp_device *dev)
{
struct rkisp_pdaf_vdev *pdaf_vdev = &dev->pdaf_vdev;
struct rkisp_vdev_node *node = &pdaf_vdev->vnode;
struct video_device *vdev = &node->vdev;
struct rkisp_pdaf_vdev *pdaf_vdev;
struct rkisp_vdev_node *node;
struct video_device *vdev;
struct media_entity *source, *sink;
int ret;
if (dev->isp_ver != ISP_V39)
if (dev->isp_ver != ISP_V39 && dev->isp_ver != ISP_V35)
return 0;
pdaf_vdev = kzalloc(sizeof(struct rkisp_pdaf_vdev), GFP_KERNEL);
if (!pdaf_vdev)
return -ENOMEM;
pdaf_vdev->dev = dev;
dev->pdaf_vdev = pdaf_vdev;
node = &pdaf_vdev->vnode;
vdev = &node->vdev;
INIT_LIST_HEAD(&pdaf_vdev->buf_queue);
spin_lock_init(&pdaf_vdev->vbq_lock);
mutex_init(&pdaf_vdev->api_lock);
@@ -419,6 +434,8 @@ int rkisp_register_pdaf_vdev(struct rkisp_device *dev)
if (ret < 0) {
v4l2_err(vdev->v4l2_dev,
"could not register Video for Linux device\n");
kfree(pdaf_vdev);
dev->pdaf_vdev = NULL;
return ret;
}
@@ -440,18 +457,25 @@ int rkisp_register_pdaf_vdev(struct rkisp_device *dev)
return 0;
unreg:
video_unregister_device(vdev);
kfree(pdaf_vdev);
dev->pdaf_vdev = NULL;
return ret;
}
void rkisp_unregister_pdaf_vdev(struct rkisp_device *dev)
{
struct rkisp_pdaf_vdev *pdaf_vdev = &dev->pdaf_vdev;
struct rkisp_vdev_node *node = &pdaf_vdev->vnode;
struct video_device *vdev = &node->vdev;
struct rkisp_pdaf_vdev *pdaf_vdev;
struct rkisp_vdev_node *node;
struct video_device *vdev;
if (dev->isp_ver != ISP_V39)
if (!dev->pdaf_vdev)
return;
pdaf_vdev = dev->pdaf_vdev;
node = &pdaf_vdev->vnode;
vdev = &node->vdev;
tasklet_kill(&pdaf_vdev->buf_done_tasklet);
media_entity_cleanup(&vdev->entity);
video_unregister_device(vdev);
kfree(pdaf_vdev);
dev->pdaf_vdev = NULL;
}

2
drivers/media/platform/rockchip/isp/isp_pdaf.h
View File

@@ -25,7 +25,7 @@ struct rkisp_pdaf_vdev {
bool stopping;
};
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V39)
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V39) || IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V35)
void rkisp_pdaf_update_buf(struct rkisp_device *dev);
void rkisp_pdaf_isr(struct rkisp_device *dev);
int rkisp_register_pdaf_vdev(struct rkisp_device *dev);

2
drivers/media/platform/rockchip/isp/isp_rockit.c
View File

@@ -315,7 +315,7 @@ int rkisp_rockit_buf_done(struct rkisp_stream *stream, int cmd, struct rkisp_buf
rockit_cfg->frame.u64PTS = ns;
rockit_cfg->frame.u32TimeRef = seq;
if (dev->isp_ver == ISP_V33)
if (dev->isp_ver == ISP_V33 || dev->isp_ver == ISP_V35)
rockit_cfg->frame.ispEncCnt =
ISP33_ISP2ENC_FRM_CNT(rkisp_read(dev, ISP3X_ISP_DEBUG1, true));
}

2
drivers/media/platform/rockchip/isp/isp_sditf.c
View File

@@ -91,6 +91,8 @@ void rkisp_sditf_reset_notify_vpss(struct rkisp_device *dev)
{
struct rkisp_sditf_device *sditf = dev->sditf_dev;
if (!sditf || !sditf->is_on || !sditf->remote_sd)
return;
v4l2_info(&dev->v4l2_dev, "%s\n", __func__);
v4l2_subdev_call(sditf->remote_sd, core, ioctl, RKISP_VPSS_RESET_NOTIFY_VPSS, NULL);
}

2
drivers/media/platform/rockchip/isp/isp_sditf.h
View File

@@ -18,7 +18,7 @@ struct rkisp_sditf_device {
bool is_on;
};
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V39)
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V39) || IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V35)
extern struct platform_driver rkisp_sditf_drv;
void rkisp_sditf_sof(struct rkisp_device *dev, u32 irq);
void rkisp_sditf_reset_notify_vpss(struct rkisp_device *dev);

61
drivers/media/platform/rockchip/isp/isp_stats.c
View File

@@ -16,6 +16,7 @@
#include "isp_stats_v32.h"
#include "isp_stats_v39.h"
#include "isp_stats_v33.h"
#include "isp_stats_v35.h"
#define STATS_NAME DRIVER_NAME "-statistics"
#define RKISP_ISP_STATS_REQ_BUFS_MIN 2
@@ -155,7 +156,7 @@ static void rkisp_stats_vb2_buf_queue(struct vb2_buffer *vb)
unsigned long flags = 0;
stats_buf->vaddr[0] = vb2_plane_vaddr(vb, 0);
if (dev->isp_ver == ISP_V32 || dev->isp_ver == ISP_V39 || dev->isp_ver == ISP_V33) {
if (dev->isp_ver == ISP_V32 || dev->isp_ver >= ISP_V33) {
struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, 0);
stats_buf->buff_addr[0] = sg_dma_address(sgt->sgl);
@@ -166,35 +167,10 @@ static void rkisp_stats_vb2_buf_queue(struct vb2_buffer *vb)
vb->vb2_queue->mem_ops->prepare(vb->planes[0].mem_priv);
}
spin_lock_irqsave(&stats_dev->rd_lock, flags);
if (dev->isp_ver == ISP_V32 && dev->is_pre_on) {
struct rkisp32_isp_stat_buffer *buf = stats_dev->stats_buf[0].vaddr;
if (dev->isp_state & ISP_START && stats_buf->vaddr[0] &&
buf && !buf->frame_id && buf->meas_type) {
dev_info(dev->dev,
"tb stat seq:%d meas_type:0x%x\n",
buf->frame_id, buf->meas_type);
memcpy(stats_buf->vaddr[0], buf, size);
buf->meas_type = 0;
vb2_set_plane_payload(vb, 0, size);
vbuf->sequence = buf->frame_id;
if (dev->is_pre_on && stats_dev->ops->stats_tb) {
if (stats_dev->ops->stats_tb(stats_dev, stats_buf) == 0) {
spin_unlock_irqrestore(&stats_dev->rd_lock, flags);
vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
return;
}
} else if (dev->isp_ver == ISP_V33 && dev->is_pre_on) {
struct rkisp33_stat_buffer *buf = stats_dev->stats_buf[0].vaddr;
if (dev->isp_state & ISP_START && stats_buf->vaddr[0] &&
buf && !buf->frame_id && buf->meas_type) {
dev_info(dev->dev,
"tb stat seq:%d meas_type:0x%x\n",
buf->frame_id, buf->meas_type);
memcpy(stats_buf->vaddr[0], buf, size);
buf->meas_type = 0;
vb2_set_plane_payload(vb, 0, size);
vbuf->sequence = buf->frame_id;
spin_unlock_irqrestore(&stats_dev->rd_lock, flags);
vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
return;
}
@@ -280,8 +256,7 @@ static int rkisp_stats_init_vb2_queue(struct vb2_queue *q,
q->drv_priv = stats_vdev;
q->ops = &rkisp_stats_vb2_ops;
if (stats_vdev->dev->isp_ver == ISP_V32 ||
stats_vdev->dev->isp_ver == ISP_V39 ||
stats_vdev->dev->isp_ver == ISP_V33) {
stats_vdev->dev->isp_ver >= ISP_V33) {
q->mem_ops = stats_vdev->dev->hw_dev->mem_ops;
if (stats_vdev->dev->hw_dev->is_dma_contig)
q->dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS;
@@ -336,6 +311,8 @@ static void rkisp_init_stats_vdev(struct rkisp_isp_stats_vdev *stats_vdev)
rkisp_init_stats_vdev_v39(stats_vdev);
else if (dev->isp_ver == ISP_V33)
rkisp_init_stats_vdev_v33(stats_vdev);
else if (dev->isp_ver == ISP_V35)
rkisp_init_stats_vdev_v35(stats_vdev);
}
static void rkisp_uninit_stats_vdev(struct rkisp_isp_stats_vdev *stats_vdev)
@@ -356,6 +333,8 @@ static void rkisp_uninit_stats_vdev(struct rkisp_isp_stats_vdev *stats_vdev)
rkisp_uninit_stats_vdev_v39(stats_vdev);
else if (dev->isp_ver == ISP_V33)
rkisp_uninit_stats_vdev_v33(stats_vdev);
else if (dev->isp_ver == ISP_V35)
rkisp_uninit_stats_vdev_v35(stats_vdev);
}
void rkisp_stats_rdbk_enable(struct rkisp_isp_stats_vdev *stats_vdev, bool en)
@@ -366,28 +345,14 @@ void rkisp_stats_rdbk_enable(struct rkisp_isp_stats_vdev *stats_vdev, bool en)
void rkisp_stats_first_ddr_config(struct rkisp_isp_stats_vdev *stats_vdev)
{
if (stats_vdev->dev->isp_ver == ISP_V20)
rkisp_stats_first_ddr_config_v2x(stats_vdev);
else if (stats_vdev->dev->isp_ver == ISP_V21)
rkisp_stats_first_ddr_config_v21(stats_vdev);
else if (stats_vdev->dev->isp_ver == ISP_V30)
rkisp_stats_first_ddr_config_v3x(stats_vdev);
else if (stats_vdev->dev->isp_ver == ISP_V32)
rkisp_stats_first_ddr_config_v32(stats_vdev);
else if (stats_vdev->dev->isp_ver == ISP_V39)
rkisp_stats_first_ddr_config_v39(stats_vdev);
else if (stats_vdev->dev->isp_ver == ISP_V33)
rkisp_stats_first_ddr_config_v33(stats_vdev);
if (stats_vdev->ops->first_ddr_cfg)
stats_vdev->ops->first_ddr_cfg(stats_vdev);
}
void rkisp_stats_next_ddr_config(struct rkisp_isp_stats_vdev *stats_vdev)
{
if (stats_vdev->dev->isp_ver == ISP_V32)
rkisp_stats_next_ddr_config_v32(stats_vdev);
else if (stats_vdev->dev->isp_ver == ISP_V39)
rkisp_stats_next_ddr_config_v39(stats_vdev);
else if (stats_vdev->dev->isp_ver == ISP_V33)
rkisp_stats_next_ddr_config_v33(stats_vdev);
if (stats_vdev->ops->next_ddr_cfg)
stats_vdev->ops->next_ddr_cfg(stats_vdev);
}
void rkisp_stats_isr(struct rkisp_isp_stats_vdev *stats_vdev,

3
drivers/media/platform/rockchip/isp/isp_stats.h
View File

@@ -35,6 +35,9 @@ struct rkisp_isp_stats_ops {
struct rkisp_isp_readout_work *meas_work);
void (*rdbk_enable)(struct rkisp_isp_stats_vdev *stats_vdev, bool en);
void (*get_stat_size)(struct rkisp_isp_stats_vdev *stats_vdev, unsigned int sizes[]);
void (*first_ddr_cfg)(struct rkisp_isp_stats_vdev *stats_vdev);
void (*next_ddr_cfg)(struct rkisp_isp_stats_vdev *stats_vdev);
int (*stats_tb)(struct rkisp_isp_stats_vdev *stats_vdev, struct rkisp_buffer *stats_buf);
};
/*

18
drivers/media/platform/rockchip/isp/isp_stats_v21.c
View File

@@ -1133,14 +1133,8 @@ rkisp_get_stat_size_v21(struct rkisp_isp_stats_vdev *stats_vdev,
stats_vdev->vdev_fmt.fmt.meta.buffersize = sizes[0];
}
static struct rkisp_isp_stats_ops rkisp_isp_stats_ops_tbl = {
.isr_hdl = rkisp_stats_isr_v21,
.send_meas = rkisp_stats_send_meas_v21,
.rdbk_enable = rkisp_stats_rdbk_enable_v21,
.get_stat_size = rkisp_get_stat_size_v21,
};
void rkisp_stats_first_ddr_config_v21(struct rkisp_isp_stats_vdev *stats_vdev)
static void
rkisp_stats_first_ddr_config_v21(struct rkisp_isp_stats_vdev *stats_vdev)
{
stats_vdev->rd_stats_from_ddr = false;
stats_vdev->priv_ops = &rkisp_stats_reg_ops_v21;
@@ -1161,6 +1155,14 @@ void rkisp_stats_first_ddr_config_v21(struct rkisp_isp_stats_vdev *stats_vdev)
}
}
static struct rkisp_isp_stats_ops rkisp_isp_stats_ops_tbl = {
.isr_hdl = rkisp_stats_isr_v21,
.send_meas = rkisp_stats_send_meas_v21,
.rdbk_enable = rkisp_stats_rdbk_enable_v21,
.get_stat_size = rkisp_get_stat_size_v21,
.first_ddr_cfg = rkisp_stats_first_ddr_config_v21,
};
void rkisp_init_stats_vdev_v21(struct rkisp_isp_stats_vdev *stats_vdev)
{
int mult = stats_vdev->dev->hw_dev->unite ? ISP_UNITE_MAX : 1;

2
drivers/media/platform/rockchip/isp/isp_stats_v21.h
View File

@@ -40,11 +40,9 @@ struct rkisp_stats_v21_ops {
};
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V21)
void rkisp_stats_first_ddr_config_v21(struct rkisp_isp_stats_vdev *stats_vdev);
void rkisp_init_stats_vdev_v21(struct rkisp_isp_stats_vdev *stats_vdev);
void rkisp_uninit_stats_vdev_v21(struct rkisp_isp_stats_vdev *stats_vdev);
#else
static inline void rkisp_stats_first_ddr_config_v21(struct rkisp_isp_stats_vdev *stats_vdev) {}
static inline void rkisp_init_stats_vdev_v21(struct rkisp_isp_stats_vdev *stats_vdev) {}
static inline void rkisp_uninit_stats_vdev_v21(struct rkisp_isp_stats_vdev *stats_vdev) {}
#endif

18
drivers/media/platform/rockchip/isp/isp_stats_v2x.c
View File

@@ -1467,14 +1467,8 @@ rkisp_get_stat_size_v2x(struct rkisp_isp_stats_vdev *stats_vdev,
stats_vdev->vdev_fmt.fmt.meta.buffersize = sizes[0];
}
static struct rkisp_isp_stats_ops rkisp_isp_stats_ops_tbl = {
.isr_hdl = rkisp_stats_isr_v2x,
.send_meas = rkisp_stats_send_meas_v2x,
.rdbk_enable = rkisp_stats_rdbk_enable_v2x,
.get_stat_size = rkisp_get_stat_size_v2x,
};
void rkisp_stats_first_ddr_config_v2x(struct rkisp_isp_stats_vdev *stats_vdev)
static void
rkisp_stats_first_ddr_config_v2x(struct rkisp_isp_stats_vdev *stats_vdev)
{
bool reg_withstream = false;
struct v4l2_subdev *sd = v4l2_get_subdev_hostdata(&stats_vdev->dev->br_dev.sd);
@@ -1499,6 +1493,14 @@ void rkisp_stats_first_ddr_config_v2x(struct rkisp_isp_stats_vdev *stats_vdev)
}
}
static struct rkisp_isp_stats_ops rkisp_isp_stats_ops_tbl = {
.isr_hdl = rkisp_stats_isr_v2x,
.send_meas = rkisp_stats_send_meas_v2x,
.rdbk_enable = rkisp_stats_rdbk_enable_v2x,
.get_stat_size = rkisp_get_stat_size_v2x,
.first_ddr_cfg = rkisp_stats_first_ddr_config_v2x,
};
void rkisp_init_stats_vdev_v2x(struct rkisp_isp_stats_vdev *stats_vdev)
{
stats_vdev->ops = &rkisp_isp_stats_ops_tbl;

2
drivers/media/platform/rockchip/isp/isp_stats_v2x.h
View File

@@ -58,11 +58,9 @@ struct rkisp_stats_v2x_ops {
};
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V20)
void rkisp_stats_first_ddr_config_v2x(struct rkisp_isp_stats_vdev *stats_vdev);
void rkisp_init_stats_vdev_v2x(struct rkisp_isp_stats_vdev *stats_vdev);
void rkisp_uninit_stats_vdev_v2x(struct rkisp_isp_stats_vdev *stats_vdev);
#else
static inline void rkisp_stats_first_ddr_config_v2x(struct rkisp_isp_stats_vdev *stats_vdev) {}
static inline void rkisp_init_stats_vdev_v2x(struct rkisp_isp_stats_vdev *stats_vdev) {}
static inline void rkisp_uninit_stats_vdev_v2x(struct rkisp_isp_stats_vdev *stats_vdev) {}
#endif

42
drivers/media/platform/rockchip/isp/isp_stats_v32.c
View File

@@ -1088,14 +1088,29 @@ rkisp_get_stat_size_v32(struct rkisp_isp_stats_vdev *stats_vdev,
stats_vdev->vdev_fmt.fmt.meta.buffersize = sizes[0];
}
static struct rkisp_isp_stats_ops rkisp_isp_stats_ops_tbl = {
.isr_hdl = rkisp_stats_isr_v32,
.send_meas = rkisp_stats_send_meas_v32,
.rdbk_enable = rkisp_stats_rdbk_enable_v32,
.get_stat_size = rkisp_get_stat_size_v32,
};
static int
rkisp_stats_tb_v32(struct rkisp_isp_stats_vdev *stats_vdev,
struct rkisp_buffer *stats_buf)
{
struct rkisp_device *dev = stats_vdev->dev;
struct rkisp32_isp_stat_buffer *buf = stats_vdev->stats_buf[0].vaddr;
u32 size = stats_vdev->vdev_fmt.fmt.meta.buffersize;
int ret = -EINVAL;
void rkisp_stats_first_ddr_config_v32(struct rkisp_isp_stats_vdev *stats_vdev)
if (dev->isp_state & ISP_START && stats_buf->vaddr[0] &&
buf && !buf->frame_id && buf->meas_type) {
dev_info(dev->dev, "tb stat seq:%d meas_type:0x%x\n",
buf->frame_id, buf->meas_type);
memcpy(stats_buf->vaddr[0], buf, size);
stats_buf->vb.sequence = buf->frame_id;
buf->meas_type = 0;
ret = 0;
}
return ret;
}
static void
rkisp_stats_first_ddr_config_v32(struct rkisp_isp_stats_vdev *stats_vdev)
{
struct rkisp_device *dev = stats_vdev->dev;
u32 size = 0, div = dev->unite_div;
@@ -1119,7 +1134,8 @@ void rkisp_stats_first_ddr_config_v32(struct rkisp_isp_stats_vdev *stats_vdev)
}
}
void rkisp_stats_next_ddr_config_v32(struct rkisp_isp_stats_vdev *stats_vdev)
static void
rkisp_stats_next_ddr_config_v32(struct rkisp_isp_stats_vdev *stats_vdev)
{
struct rkisp_hw_dev *hw = stats_vdev->dev->hw_dev;
@@ -1130,6 +1146,16 @@ void rkisp_stats_next_ddr_config_v32(struct rkisp_isp_stats_vdev *stats_vdev)
rkisp_stats_update_buf(stats_vdev);
}
static struct rkisp_isp_stats_ops rkisp_isp_stats_ops_tbl = {
.isr_hdl = rkisp_stats_isr_v32,
.send_meas = rkisp_stats_send_meas_v32,
.rdbk_enable = rkisp_stats_rdbk_enable_v32,
.get_stat_size = rkisp_get_stat_size_v32,
.stats_tb = rkisp_stats_tb_v32,
.first_ddr_cfg = rkisp_stats_first_ddr_config_v32,
.next_ddr_cfg = rkisp_stats_next_ddr_config_v32,
};
void rkisp_init_stats_vdev_v32(struct rkisp_isp_stats_vdev *stats_vdev)
{
if (stats_vdev->dev->isp_ver == ISP_V32) {

4
drivers/media/platform/rockchip/isp/isp_stats_v32.h
View File

@@ -40,13 +40,9 @@ struct rkisp_stats_ops_v32 {
};
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V32)
void rkisp_stats_first_ddr_config_v32(struct rkisp_isp_stats_vdev *stats_vdev);
void rkisp_stats_next_ddr_config_v32(struct rkisp_isp_stats_vdev *stats_vdev);
void rkisp_init_stats_vdev_v32(struct rkisp_isp_stats_vdev *stats_vdev);
void rkisp_uninit_stats_vdev_v32(struct rkisp_isp_stats_vdev *stats_vdev);
#else
static inline void rkisp_stats_first_ddr_config_v32(struct rkisp_isp_stats_vdev *stats_vdev) {}
static inline void rkisp_stats_next_ddr_config_v32(struct rkisp_isp_stats_vdev *stats_vdev) {}
static inline void rkisp_init_stats_vdev_v32(struct rkisp_isp_stats_vdev *stats_vdev) {}
static inline void rkisp_uninit_stats_vdev_v32(struct rkisp_isp_stats_vdev *stats_vdev) {}
#endif

40
drivers/media/platform/rockchip/isp/isp_stats_v33.c
View File

@@ -504,13 +504,29 @@ rkisp_get_stat_size_v33(struct rkisp_isp_stats_vdev *stats_vdev,
stats_vdev->vdev_fmt.fmt.meta.buffersize = sizes[0];
}
static struct rkisp_isp_stats_ops rkisp_isp_stats_ops_tbl = {
.isr_hdl = rkisp_stats_isr_v33,
.send_meas = rkisp_stats_send_meas_v33,
.get_stat_size = rkisp_get_stat_size_v33,
};
static int
rkisp_stats_tb_v33(struct rkisp_isp_stats_vdev *stats_vdev,
struct rkisp_buffer *stats_buf)
{
struct rkisp_device *dev = stats_vdev->dev;
struct rkisp33_stat_buffer *buf = stats_vdev->stats_buf[0].vaddr;
u32 size = stats_vdev->vdev_fmt.fmt.meta.buffersize;
int ret = -EINVAL;
void rkisp_stats_first_ddr_config_v33(struct rkisp_isp_stats_vdev *stats_vdev)
if (dev->isp_state & ISP_START && stats_buf->vaddr[0] &&
buf && !buf->frame_id && buf->meas_type) {
dev_info(dev->dev, "tb stat seq:%d meas_type:0x%x\n",
buf->frame_id, buf->meas_type);
memcpy(stats_buf->vaddr[0], buf, size);
stats_buf->vb.sequence = buf->frame_id;
buf->meas_type = 0;
ret = 0;
}
return ret;
}
static void
rkisp_stats_first_ddr_config_v33(struct rkisp_isp_stats_vdev *stats_vdev)
{
struct rkisp_device *dev = stats_vdev->dev;
u32 val, size = 0, div = dev->unite_div;
@@ -539,7 +555,8 @@ void rkisp_stats_first_ddr_config_v33(struct rkisp_isp_stats_vdev *stats_vdev)
}
}
void rkisp_stats_next_ddr_config_v33(struct rkisp_isp_stats_vdev *stats_vdev)
static void
rkisp_stats_next_ddr_config_v33(struct rkisp_isp_stats_vdev *stats_vdev)
{
struct rkisp_device *dev = stats_vdev->dev;
struct rkisp_hw_dev *hw = dev->hw_dev;
@@ -551,6 +568,15 @@ void rkisp_stats_next_ddr_config_v33(struct rkisp_isp_stats_vdev *stats_vdev)
rkisp_stats_update_buf(stats_vdev);
}
static struct rkisp_isp_stats_ops rkisp_isp_stats_ops_tbl = {
.isr_hdl = rkisp_stats_isr_v33,
.send_meas = rkisp_stats_send_meas_v33,
.get_stat_size = rkisp_get_stat_size_v33,
.stats_tb = rkisp_stats_tb_v33,
.first_ddr_cfg = rkisp_stats_first_ddr_config_v33,
.next_ddr_cfg = rkisp_stats_next_ddr_config_v33,
};
void rkisp_init_stats_vdev_v33(struct rkisp_isp_stats_vdev *stats_vdev)
{
stats_vdev->ops = &rkisp_isp_stats_ops_tbl;

4
drivers/media/platform/rockchip/isp/isp_stats_v33.h
View File

@@ -12,13 +12,9 @@
struct rkisp_isp_stats_vdev;
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V33)
void rkisp_stats_first_ddr_config_v33(struct rkisp_isp_stats_vdev *stats_vdev);
void rkisp_stats_next_ddr_config_v33(struct rkisp_isp_stats_vdev *stats_vdev);
void rkisp_init_stats_vdev_v33(struct rkisp_isp_stats_vdev *stats_vdev);
void rkisp_uninit_stats_vdev_v33(struct rkisp_isp_stats_vdev *stats_vdev);
#else
static inline void rkisp_stats_first_ddr_config_v33(struct rkisp_isp_stats_vdev *stats_vdev) {}
static inline void rkisp_stats_next_ddr_config_v33(struct rkisp_isp_stats_vdev *stats_vdev) {}
static inline void rkisp_init_stats_vdev_v33(struct rkisp_isp_stats_vdev *stats_vdev) {}
static inline void rkisp_uninit_stats_vdev_v33(struct rkisp_isp_stats_vdev *stats_vdev) {}
#endif

636
drivers/media/platform/rockchip/isp/isp_stats_v35.c Normal file
View File

@@ -0,0 +1,636 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright (c) 2025 Rockchip Electronics Co., Ltd. */
#include <linux/delay.h>
#include <linux/kfifo.h>
#include <linux/rk-isp32-config.h>
#include <media/v4l2-common.h>
#include <media/v4l2-ioctl.h>
#include <media/videobuf2-core.h>
#include "dev.h"
#include "regs.h"
#include "common.h"
#include "isp_stats.h"
#include "isp_stats_v35.h"
#include "isp_params_v35.h"
#define ISP35_3A_MEAS_DONE BIT(31)
static void isp3_module_done(struct rkisp_isp_stats_vdev *stats_vdev, u32 reg, u32 value)
{
void __iomem *base = stats_vdev->dev->hw_dev->base_addr;
writel(value, base + reg);
}
static u32 isp3_stats_read(struct rkisp_isp_stats_vdev *stats_vdev, u32 addr)
{
return rkisp_read(stats_vdev->dev, addr, true);
}
static void isp3_stats_write(struct rkisp_isp_stats_vdev *stats_vdev,
u32 addr, u32 value)
{
rkisp_write(stats_vdev->dev, addr, value, true);
}
static int
rkisp_stats_get_sharp_stats(struct rkisp_isp_stats_vdev *stats_vdev,
struct rkisp35_stat_buffer *pbuf)
{
struct isp33_sharp_stat *sharp;
u32 i, val;
if (!pbuf)
return 0;
val = isp3_stats_read(stats_vdev, ISP3X_SHARP_EN);
if (val & 0x1) {
sharp = &pbuf->stat.sharp;
for (i = 0; i < ISP35_SHARP_NOISE_CURVE_NUM / 2; i++) {
val = isp3_stats_read(stats_vdev, ISP33_SHARP_NOISE_CURVE0 + i * 4);
sharp->noise_curve[i * 2] = val & 0x7ff;
sharp->noise_curve[i * 2 + 1] = (val >> 16) & 0x7ff;
}
val = isp3_stats_read(stats_vdev, ISP33_SHARP_NOISE_CURVE8);
sharp->noise_curve[i * 2] = val & 0x7ff;
pbuf->meas_type |= ISP35_STAT_SHARP;
}
return 0;
}
static int
rkisp_stats_get_bay3d_stats(struct rkisp_isp_stats_vdev *stats_vdev,
struct rkisp35_stat_buffer *pbuf)
{
struct isp33_bay3d_stat *bay3d;
u32 i, val;
if (!pbuf)
return 0;
val = isp3_stats_read(stats_vdev, ISP33_BAY3D_CTRL0);
if (val & 0x1) {
bay3d = &pbuf->stat.bay3d;
val = isp3_stats_read(stats_vdev, ISP33_BAY3D_TNRSUM);
bay3d->sigma_num = val;
for (i = 0; i < ISP35_BAY3D_TNRSIG_NUM / 2; i++) {
val = isp3_stats_read(stats_vdev, ISP33_BAY3D_TNRYO0 + i * 4);
bay3d->sigma_y[i * 2] = val & 0xfff;
bay3d->sigma_y[i * 2 + 1] = (val >> 16) & 0xfff;
}
pbuf->meas_type |= ISP35_STAT_BAY3D;
}
return 0;
}
static int
rkisp_stats_get_hist_stats(struct rkisp_isp_stats_vdev *stats_vdev,
struct rkisp35_stat_buffer *pbuf)
{
struct rkisp_device *dev = stats_vdev->dev;
struct rkisp_isp_params_vdev *params = &dev->params_vdev;
struct rkisp_isp_params_val_v35 *priv_val = params->priv_val;
struct isp35_isp_params_cfg *params_rec = params->isp35_params + dev->unite_index;
struct isp33_hist_cfg *arg_rec = &params_rec->others.hist_cfg;
struct isp33_hist_stat *hist;
int val, i, j, timeout;
val = isp3_stats_read(stats_vdev, ISP33_HIST_CTRL);
if (val & 0x1) {
val = isp3_stats_read(stats_vdev, ISP33_HIST_STAB);
arg_rec->stab_frame_cnt0 = val & 0xf;
arg_rec->stab_frame_cnt1 = (val & 0xf0) >> 4;
for (i = 0; i < priv_val->hist_blk_num; i++) {
val = ISP33_IIR_RD_ID(i) | ISP33_IIR_RD_P;
isp3_stats_write(stats_vdev, ISP33_HIST_RW, val);
timeout = 5;
while (timeout--) {
val = isp3_stats_read(stats_vdev, ISP33_HIST_RW);
if (val & ISP33_IIR_RDATA_VAL)
break;
udelay(2);
}
if (timeout < 0) {
v4l2_warn(&dev->v4l2_dev, "%s hist read:%d timeout\n", __func__, i);
return 0;
}
for (j = 0; j < ISP35_HIST_IIR_NUM / 2; j++) {
val = isp3_stats_read(stats_vdev, ISP33_HIST_IIR0 + 4 * j);
arg_rec->iir[i][2 * j] = val & 0x3FF;
arg_rec->iir[i][2 * j + 1] = val >> 16;
}
}
if (dev->is_frm_rd)
arg_rec->iir_wr = true;
if (pbuf) {
hist = &pbuf->stat.hist;
memcpy(hist->iir, arg_rec->iir, sizeof(hist->iir));
pbuf->meas_type |= ISP35_STAT_HIST;
}
}
return 0;
}
static int
rkisp_stats_get_enh_stats(struct rkisp_isp_stats_vdev *stats_vdev,
struct rkisp35_stat_buffer *pbuf)
{
struct rkisp_device *dev = stats_vdev->dev;
struct rkisp_isp_params_vdev *params = &dev->params_vdev;
struct rkisp_isp_params_val_v35 *priv_val = params->priv_val;
struct isp35_isp_params_cfg *params_rec = params->isp35_params + dev->unite_index;
struct isp33_enh_cfg *arg_rec = &params_rec->others.enh_cfg;
struct isp33_enh_stat *enh;
int val, i, j, timeout;
val = isp3_stats_read(stats_vdev, ISP33_ENH_CTRL);
if (val & 0x1) {
val = isp3_stats_read(stats_vdev, ISP33_ENH_PRE_FRAME);
arg_rec->pre_wet_frame_cnt0 = val & 0xf;
arg_rec->pre_wet_frame_cnt1 = (val & 0xf0) >> 4;
for (i = 0; i < priv_val->enh_row; i++) {
val = ISP33_IIR_RD_ID(i) | ISP33_IIR_RD_P;
isp3_stats_write(stats_vdev, ISP33_ENH_IIR_RW, val);
timeout = 5;
while (timeout--) {
val = isp3_stats_read(stats_vdev, ISP33_ENH_IIR_RW);
if (val & ISP33_IIR_RDATA_VAL)
break;
udelay(2);
}
if (timeout < 0) {
v4l2_warn(&dev->v4l2_dev, "%s enh read:%d timeout\n", __func__, i);
return 0;
}
for (j = 0; j < priv_val->enh_col / 4; j++) {
val = isp3_stats_read(stats_vdev, ISP33_ENH_IIR0 + 4 * j);
arg_rec->iir[i][4 * j] = val & 0xFF;
arg_rec->iir[i][4 * j + 1] = (val & 0xff00) >> 8;
arg_rec->iir[i][4 * j + 2] = (val & 0xff0000) >> 16;
arg_rec->iir[i][4 * j + 3] = (val & 0xff000000) >> 24;
}
}
if (dev->is_frm_rd)
arg_rec->iir_wr = true;
if (pbuf) {
enh = &pbuf->stat.enh;
memcpy(enh->iir, arg_rec->iir, sizeof(enh->iir));
pbuf->meas_type |= ISP35_STAT_ENH;
}
}
return 0;
}
static int
rkisp_stats_update_buf(struct rkisp_isp_stats_vdev *stats_vdev)
{
struct rkisp_device *dev = stats_vdev->dev;
struct rkisp_buffer *buf;
unsigned long flags = 0;
u32 size = stats_vdev->vdev_fmt.fmt.meta.buffersize / dev->unite_div;
u32 val, addr = 0, offset = 0;
int i, ret = 0;
spin_lock_irqsave(&stats_vdev->rd_lock, flags);
if (!stats_vdev->nxt_buf && !list_empty(&stats_vdev->stat)) {
buf = list_first_entry(&stats_vdev->stat,
struct rkisp_buffer, queue);
list_del(&buf->queue);
stats_vdev->nxt_buf = buf;
}
spin_unlock_irqrestore(&stats_vdev->rd_lock, flags);
if (stats_vdev->nxt_buf) {
addr = stats_vdev->nxt_buf->buff_addr[0];
if (!dev->hw_dev->is_single) {
stats_vdev->cur_buf = stats_vdev->nxt_buf;
stats_vdev->nxt_buf = NULL;
}
} else if (stats_vdev->stats_buf[0].mem_priv) {
addr = stats_vdev->stats_buf[0].dma_addr;
} else {
ret = -EINVAL;
}
if (addr) {
for (i = 0; i < dev->unite_div; i++) {
val = addr + i * size;
rkisp_idx_write(dev, ISP39_W3A_AEBIG_ADDR, val, i, false);
offset = sizeof(struct isp33_rawae_stat) +
sizeof(struct isp33_rawhist_stat);
val += offset;
rkisp_idx_write(dev, ISP39_W3A_AE0_ADDR, val, i, false);
val += offset;
rkisp_idx_write(dev, ISP39_W3A_AF_ADDR, val, i, false);
offset = sizeof(struct isp39_rawaf_stat);
val += offset;
rkisp_idx_write(dev, ISP39_W3A_AWB_ADDR, val, i, false);
}
v4l2_dbg(4, rkisp_debug, &dev->v4l2_dev,
"%s BASE:0x%x SHD AEBIG:0x%x AE0:0x%x AF:0x%x AWB:0x%x\n",
__func__, addr,
isp3_stats_read(stats_vdev, ISP39_W3A_AEBIG_ADDR_SHD),
isp3_stats_read(stats_vdev, ISP39_W3A_AE0_ADDR_SHD),
isp3_stats_read(stats_vdev, ISP39_W3A_AF_ADDR_SHD),
isp3_stats_read(stats_vdev, ISP39_W3A_AWB_ADDR_SHD));
}
return ret;
}
static void
rkisp_stats_get_aiawb_stats(struct rkisp_isp_stats_vdev *stats_vdev,
struct rkisp35_stat_buffer *pbuf)
{
struct rkisp_device *dev = stats_vdev->dev;
struct rkisp_isp_params_vdev *params_vdev = &dev->params_vdev;
struct rkisp_isp_params_val_v35 *priv_val = params_vdev->priv_val;
u32 ctrl = rkisp_read(dev, ISP35_AIAWB_CTRL0, false);
u32 buf_idx, val;
if (!pbuf || !(ctrl & ISP35_AIAWB_EN) || !priv_val->buf_aiawb_cnt)
return;
pbuf->meas_type |= ISP35_STAT_AIAWB;
buf_idx = priv_val->buf_aiawb_idx;
pbuf->stat.buf_aiawb_index = priv_val->buf_aiawb[buf_idx].index;
buf_idx = (buf_idx + 1) % priv_val->buf_aiawb_cnt;
val = priv_val->buf_aiawb[buf_idx].dma_addr;
rkisp_write(dev, ISP35_AIAWB_WR_BASE, val, false);
rkisp_write(dev, ISP35_AIAWB_CTRL0, ctrl | ISP35_AIAWB_SELF_UPD, false);
priv_val->buf_aiawb_idx = buf_idx;
}
static void
rkisp_stats_get_awbsync_stats(struct rkisp_isp_stats_vdev *stats_vdev,
struct rkisp35_stat_buffer *pbuf)
{
struct isp35_awbsync_stat *awbsync;
u32 ctrl = isp3_stats_read(stats_vdev, ISP35_AWBSYNC_CTRL);
u64 msb, lsb;
int i;
if (!(ctrl & ISP35_3A_MEAS_DONE)) {
v4l2_dbg(1, rkisp_debug, &stats_vdev->dev->v4l2_dev,
"%s fail, ctrl:0x%x\n", __func__, ctrl);
return;
}
if (!pbuf)
goto out;
awbsync = &pbuf->stat.awbsync;
for (i = 0; i < ISP35_AWBSYNC_WIN_MAX; i++) {
msb = isp3_stats_read(stats_vdev, ISP35_AWBSYNC_WIN0_SUMP + i * 0x10);
awbsync->sump[i] = msb & 0x3ffffff;
lsb = isp3_stats_read(stats_vdev, ISP35_AWBSYNC_WIN0_SUMR + i * 0x10);
awbsync->sumr[i] = lsb | ((msb & 0xc0000000) << 2);
lsb = isp3_stats_read(stats_vdev, ISP35_AWBSYNC_WIN0_SUMG + i * 0x10);
awbsync->sumg[i] = lsb | ((msb & 0x30000000) << 4);
lsb = isp3_stats_read(stats_vdev, ISP35_AWBSYNC_WIN0_SUMB + i * 0x10);
awbsync->sumg[i] = lsb | ((msb & 0xc000000) << 6);
}
pbuf->meas_type |= ISP35_STAT_AWBSYNC;
out:
isp3_module_done(stats_vdev, ISP35_AWBSYNC_CTRL, ctrl);
}
static void
rkisp_stats_info2ddr(struct rkisp_isp_stats_vdev *stats_vdev,
struct rkisp35_stat_buffer *pbuf)
{
struct rkisp_device *dev = stats_vdev->dev;
struct rkisp_isp_params_val_v35 *priv_val;
struct rkisp_dummy_buffer *buf;
int idx, buf_fd = -1;
u32 reg = 0, ctrl, mask;
if (dev->is_aiisp_en)
return;
priv_val = dev->params_vdev.priv_val;
if (!priv_val->buf_info_owner && priv_val->buf_info_idx >= 0) {
priv_val->buf_info_idx = -1;
rkisp_clear_bits(dev, ISP3X_GAIN_CTRL, ISP3X_GAIN_2DDR_EN, false);
rkisp_clear_bits(dev, ISP3X_RAWAWB_CTRL, ISP32_RAWAWB_2DDR_PATH_EN, false);
return;
}
if (priv_val->buf_info_owner == RKISP_INFO2DRR_OWNER_GAIN) {
reg = ISP3X_GAIN_CTRL;
ctrl = ISP3X_GAIN_2DDR_EN;
mask = ISP3X_GAIN_2DDR_EN;
} else {
reg = ISP3X_RAWAWB_CTRL;
ctrl = ISP32_RAWAWB_2DDR_PATH_EN;
mask = ISP32_RAWAWB_2DDR_PATH_EN | ISP32_RAWAWB_2DDR_PATH_DS;
}
idx = priv_val->buf_info_idx;
if (idx >= 0) {
buf = &priv_val->buf_info[idx];
rkisp_finish_buffer(dev, buf);
v4l2_dbg(4, rkisp_debug, &dev->v4l2_dev,
"%s data:0x%x 0x%x:0x%x\n", __func__,
*(u32 *)buf->vaddr, reg, rkisp_read(dev, reg, true));
if (*(u32 *)buf->vaddr != RKISP_INFO2DDR_BUF_INIT && pbuf &&
(reg != ISP3X_RAWAWB_CTRL ||
!(rkisp_read(dev, reg, true) & ISP32_RAWAWB_2DDR_PATH_ERR))) {
pbuf->stat.info2ddr.buf_fd = buf->dma_fd;
pbuf->stat.info2ddr.owner = priv_val->buf_info_owner;
pbuf->meas_type |= ISP35_STAT_INFO2DDR;
buf_fd = buf->dma_fd;
} else if (reg == ISP3X_RAWAWB_CTRL &&
rkisp_read(dev, reg, true) & ISP32_RAWAWB_2DDR_PATH_ERR) {
v4l2_warn(&dev->v4l2_dev, "rawawb2ddr path error idx:%d\n", idx);
} else {
u32 v0 = rkisp_read(dev, reg, false);
u32 v1 = rkisp_read_reg_cache(dev, reg);
if ((v0 & mask) != (v1 & mask))
rkisp_write(dev, reg, v0 | (v1 & mask), false);
}
if (buf_fd == -1)
return;
}
/* get next unused buf to hw */
for (idx = 0; idx < priv_val->buf_info_cnt; idx++) {
buf = &priv_val->buf_info[idx];
if (*(u32 *)buf->vaddr == RKISP_INFO2DDR_BUF_INIT)
break;
}
if (idx == priv_val->buf_info_cnt) {
rkisp_clear_bits(dev, reg, ctrl, false);
priv_val->buf_info_idx = -1;
} else {
buf = &priv_val->buf_info[idx];
rkisp_write(dev, ISP3X_MI_GAIN_WR_BASE, buf->dma_addr, false);
if (dev->hw_dev->is_single)
rkisp_write(dev, ISP3X_MI_WR_CTRL2, ISP3X_GAINSELF_UPD, true);
if (priv_val->buf_info_idx < 0)
rkisp_set_bits(dev, reg, 0, ctrl, false);
priv_val->buf_info_idx = idx;
}
}
static void
rkisp_stats_send_meas_v35(struct rkisp_isp_stats_vdev *stats_vdev,
struct rkisp_isp_readout_work *meas_work)
{
struct rkisp_isp_params_vdev *params_vdev = &stats_vdev->dev->params_vdev;
struct rkisp_device *dev = stats_vdev->dev;
struct rkisp_buffer *cur_buf = stats_vdev->cur_buf;
struct rkisp35_stat_buffer *cur_stat_buf = NULL;
u32 size = stats_vdev->vdev_fmt.fmt.meta.buffersize;
u32 cur_frame_id = meas_work->frame_id;
bool is_dummy = false;
unsigned long flags = 0;
if (!stats_vdev->rdbk_drop) {
if (!cur_buf && stats_vdev->stats_buf[0].mem_priv) {
rkisp_finish_buffer(stats_vdev->dev, &stats_vdev->stats_buf[0]);
cur_stat_buf = stats_vdev->stats_buf[0].vaddr;
cur_stat_buf->frame_id = cur_frame_id;
cur_stat_buf->params_id = params_vdev->cur_frame_id;
is_dummy = true;
} else if (cur_buf) {
cur_stat_buf = cur_buf->vaddr[0];
cur_stat_buf->frame_id = cur_frame_id;
cur_stat_buf->params_id = params_vdev->cur_frame_id;
}
/* buffer done when frame of right handle */
if (dev->unite_div > ISP_UNITE_DIV1) {
if (dev->unite_index == ISP_UNITE_LEFT) {
cur_buf = NULL;
is_dummy = false;
} else if (cur_stat_buf) {
cur_stat_buf = (void *)cur_stat_buf + size / 2;
cur_stat_buf->frame_id = cur_frame_id;
cur_stat_buf->params_id = params_vdev->cur_frame_id;
}
}
if (dev->unite_div < ISP_UNITE_DIV2 || dev->unite_index == ISP_UNITE_RIGHT) {
/* config buf for next frame */
stats_vdev->cur_buf = NULL;
if (stats_vdev->nxt_buf) {
stats_vdev->cur_buf = stats_vdev->nxt_buf;
stats_vdev->nxt_buf = NULL;
}
rkisp_stats_update_buf(stats_vdev);
}
} else {
cur_buf = NULL;
}
if (cur_stat_buf) {
cur_stat_buf->stat.buf_aiawb_index = -1;
cur_stat_buf->stat.info2ddr.buf_fd = -1;
cur_stat_buf->stat.info2ddr.owner = 0;
}
if (meas_work->isp3a_ris & ISP3X_3A_RAWAWB && cur_stat_buf)
cur_stat_buf->meas_type |= ISP35_STAT_RAWAWB;
if (meas_work->isp3a_ris & ISP3X_3A_RAWAF && cur_stat_buf)
cur_stat_buf->meas_type |= ISP35_STAT_RAWAF;
if (meas_work->isp3a_ris & ISP3X_3A_RAWAE_BIG && cur_stat_buf)
cur_stat_buf->meas_type |= ISP35_STAT_RAWAE3;
if (meas_work->isp3a_ris & ISP3X_3A_RAWHIST_BIG && cur_stat_buf)
cur_stat_buf->meas_type |= ISP35_STAT_RAWHST3;
if (meas_work->isp3a_ris & ISP3X_3A_RAWAE_CH0 && cur_stat_buf)
cur_stat_buf->meas_type |= ISP35_STAT_RAWAE0;
if (meas_work->isp3a_ris & ISP3X_3A_RAWHIST_CH0 && cur_stat_buf)
cur_stat_buf->meas_type |= ISP35_STAT_RAWHST0;
if (meas_work->isp3a_ris & ISP35_AIAWB_DONE && cur_stat_buf)
rkisp_stats_get_aiawb_stats(stats_vdev, cur_stat_buf);
if (meas_work->isp3a_ris & ISP35_AWBSYNC_DONE && cur_stat_buf)
rkisp_stats_get_awbsync_stats(stats_vdev, cur_stat_buf);
if (meas_work->isp_ris & ISP3X_FRAME) {
rkisp_stats_get_bay3d_stats(stats_vdev, cur_stat_buf);
rkisp_stats_get_sharp_stats(stats_vdev, cur_stat_buf);
rkisp_stats_get_enh_stats(stats_vdev, cur_stat_buf);
rkisp_stats_get_hist_stats(stats_vdev, cur_stat_buf);
}
if (cur_stat_buf && (dev->is_first_double || dev->is_wait_aiq)) {
cur_stat_buf->meas_type |= ISP35_STAT_RTT_FST;
dev_info(dev->dev, "stats seq:%d meas_type:0x%x for fast\n",
cur_frame_id, cur_stat_buf->meas_type);
}
if (is_dummy) {
spin_lock_irqsave(&stats_vdev->rd_lock, flags);
if (!list_empty(&stats_vdev->stat)) {
cur_buf = list_first_entry(&stats_vdev->stat, struct rkisp_buffer, queue);
list_del(&cur_buf->queue);
}
spin_unlock_irqrestore(&stats_vdev->rd_lock, flags);
if (cur_buf) {
memcpy(cur_buf->vaddr[0], stats_vdev->stats_buf[0].vaddr, size);
cur_stat_buf = cur_buf->vaddr[0];
}
}
if (cur_buf && cur_stat_buf) {
cur_stat_buf->frame_id = cur_frame_id;
cur_stat_buf->params_id = params_vdev->cur_frame_id;
cur_stat_buf->stat.info2ddr.buf_fd = -1;
cur_stat_buf->stat.info2ddr.owner = 0;
rkisp_stats_info2ddr(stats_vdev, cur_stat_buf);
vb2_set_plane_payload(&cur_buf->vb.vb2_buf, 0, size);
cur_buf->vb.sequence = cur_frame_id;
cur_buf->vb.vb2_buf.timestamp = meas_work->timestamp;
vb2_buffer_done(&cur_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
}
v4l2_dbg(4, rkisp_debug, &stats_vdev->dev->v4l2_dev,
"%s seq:%d params_id:%d ris:0x%x buf:%p meas_type:0x%x aiawb(fd:%d 0x%x)\n",
__func__, cur_frame_id, params_vdev->cur_frame_id, meas_work->isp3a_ris,
cur_buf, !cur_stat_buf ? 0 : cur_stat_buf->meas_type,
!cur_stat_buf ? -1 : cur_stat_buf->stat.buf_aiawb_index,
isp3_stats_read(stats_vdev, ISP35_AIAWB_WR_BASE_SHD));
}
static void
rkisp_stats_isr_v35(struct rkisp_isp_stats_vdev *stats_vdev,
u32 isp_ris, u32 isp3a_ris)
{
struct rkisp_isp_readout_work work;
u32 cur_frame_id, isp_mis_tmp = 0;
u32 temp_isp3a_ris;
rkisp_dmarx_get_frame(stats_vdev->dev, &cur_frame_id, NULL, NULL, true);
temp_isp3a_ris = isp3_stats_read(stats_vdev, ISP3X_ISP_3A_RIS);
isp_mis_tmp = temp_isp3a_ris;
if (isp_mis_tmp)
isp3_stats_write(stats_vdev, ISP3X_ISP_3A_ICR, isp_mis_tmp);
rkisp_pdaf_isr(stats_vdev->dev);
if (isp_ris & ISP3X_FRAME) {
work.readout = RKISP_ISP_READOUT_MEAS;
work.frame_id = cur_frame_id;
work.isp_ris = isp_ris;
work.isp3a_ris = temp_isp3a_ris;
work.timestamp = ktime_get_ns();
rkisp_stats_send_meas_v35(stats_vdev, &work);
}
}
static void
rkisp_get_stat_size_v35(struct rkisp_isp_stats_vdev *stats_vdev,
unsigned int sizes[])
{
int mult = stats_vdev->dev->unite_div;
sizes[0] = ALIGN(sizeof(struct rkisp35_stat_buffer), 16);
sizes[0] *= mult;
stats_vdev->vdev_fmt.fmt.meta.buffersize = sizes[0];
}
static int
rkisp_stats_tb_v35(struct rkisp_isp_stats_vdev *stats_vdev,
struct rkisp_buffer *stats_buf)
{
struct rkisp_device *dev = stats_vdev->dev;
struct rkisp35_stat_buffer *buf = stats_vdev->stats_buf[0].vaddr;
u32 size = stats_vdev->vdev_fmt.fmt.meta.buffersize;
int ret = -EINVAL;
if (dev->isp_state & ISP_START && stats_buf->vaddr[0] &&
buf && !buf->frame_id && buf->meas_type) {
dev_info(dev->dev, "tb stat seq:%d meas_type:0x%x\n",
buf->frame_id, buf->meas_type);
memcpy(stats_buf->vaddr[0], buf, size);
stats_buf->vb.sequence = buf->frame_id;
buf->meas_type = 0;
ret = 0;
}
return ret;
}
static void
rkisp_stats_first_ddr_config_v35(struct rkisp_isp_stats_vdev *stats_vdev)
{
struct rkisp_device *dev = stats_vdev->dev;
struct rkisp_pdaf_vdev *pdaf_vdev = dev->pdaf_vdev;
u32 val, size = 0, div = dev->unite_div;
if (dev->isp_sdev.in_fmt.fmt_type == FMT_YUV)
return;
rkisp_get_stat_size_v35(stats_vdev, &size);
stats_vdev->stats_buf[0].is_need_vaddr = true;
stats_vdev->stats_buf[0].size = size;
if (rkisp_alloc_buffer(dev, &stats_vdev->stats_buf[0]))
v4l2_warn(&dev->v4l2_dev, "stats alloc buf fail\n");
else
memset(stats_vdev->stats_buf[0].vaddr, 0, size);
if (rkisp_stats_update_buf(stats_vdev) < 0) {
v4l2_err(&dev->v4l2_dev, "no stats buf to enable w3a\n");
return;
}
if (dev->hw_dev->is_single)
rkisp_unite_set_bits(dev, ISP3X_SWS_CFG, 0, ISP3X_3A_DDR_WRITE_EN, false);
val = rkisp_read(dev, ISP39_W3A_CTRL0, false);
val |= ISP39_W3A_EN | ISP39_W3A_AUTO_CLR_EN | ISP39_W3A_FORCE_UPD;
if (pdaf_vdev && pdaf_vdev->streaming) {
val |= ISP39_W3A_PDAF_EN;
rkisp_pdaf_update_buf(dev);
if (pdaf_vdev->next_buf) {
pdaf_vdev->curr_buf = pdaf_vdev->next_buf;
pdaf_vdev->next_buf = NULL;
}
}
rkisp_unite_write(dev, ISP39_W3A_CTRL0, val, false);
rkisp_unite_write(dev, ISP39_W3A_WR_SIZE, size / div, false);
if (stats_vdev->nxt_buf) {
stats_vdev->cur_buf = stats_vdev->nxt_buf;
stats_vdev->nxt_buf = NULL;
}
}
static void
rkisp_stats_next_ddr_config_v35(struct rkisp_isp_stats_vdev *stats_vdev)
{
struct rkisp_device *dev = stats_vdev->dev;
struct rkisp_hw_dev *hw = dev->hw_dev;
struct rkisp_pdaf_vdev *pdaf_vdev = dev->pdaf_vdev;
if (!stats_vdev->streamon || dev->isp_sdev.in_fmt.fmt_type == FMT_YUV)
return;
/* pingpong buf */
if (hw->is_single) {
rkisp_stats_update_buf(stats_vdev);
if (pdaf_vdev && pdaf_vdev->streaming)
rkisp_pdaf_update_buf(dev);
}
}
static struct rkisp_isp_stats_ops rkisp_isp_stats_ops_tbl = {
.isr_hdl = rkisp_stats_isr_v35,
.get_stat_size = rkisp_get_stat_size_v35,
.stats_tb = rkisp_stats_tb_v35,
.first_ddr_cfg = rkisp_stats_first_ddr_config_v35,
.next_ddr_cfg = rkisp_stats_next_ddr_config_v35,
};
void rkisp_init_stats_vdev_v35(struct rkisp_isp_stats_vdev *stats_vdev)
{
stats_vdev->ops = &rkisp_isp_stats_ops_tbl;
}
void rkisp_uninit_stats_vdev_v35(struct rkisp_isp_stats_vdev *stats_vdev)
{
}

19
drivers/media/platform/rockchip/isp/isp_stats_v35.h Normal file
View File

@@ -0,0 +1,19 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2025 Rockchip Electronics Co., Ltd. */
#ifndef _RKISP_STATS_V35_H
#define _RKISP_STATS_V35_H
#define ISP35_RD_STATS_BUF_SIZE 0x10000
struct rkisp_isp_stats_vdev;
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V35)
void rkisp_init_stats_vdev_v35(struct rkisp_isp_stats_vdev *stats_vdev);
void rkisp_uninit_stats_vdev_v35(struct rkisp_isp_stats_vdev *stats_vdev);
#else
static inline void rkisp_init_stats_vdev_v35(struct rkisp_isp_stats_vdev *stats_vdev) {}
static inline void rkisp_uninit_stats_vdev_v35(struct rkisp_isp_stats_vdev *stats_vdev) {}
#endif
#endif /* _RKISP_STATS_V35_H */

26
drivers/media/platform/rockchip/isp/isp_stats_v39.c
View File

@@ -477,15 +477,11 @@ rkisp_get_stat_size_v39(struct rkisp_isp_stats_vdev *stats_vdev,
stats_vdev->vdev_fmt.fmt.meta.buffersize = sizes[0];
}
static struct rkisp_isp_stats_ops rkisp_isp_stats_ops_tbl = {
.isr_hdl = rkisp_stats_isr_v39,
.get_stat_size = rkisp_get_stat_size_v39,
};
void rkisp_stats_first_ddr_config_v39(struct rkisp_isp_stats_vdev *stats_vdev)
static void
rkisp_stats_first_ddr_config_v39(struct rkisp_isp_stats_vdev *stats_vdev)
{
struct rkisp_device *dev = stats_vdev->dev;
struct rkisp_pdaf_vdev *pdaf_vdev = &dev->pdaf_vdev;
struct rkisp_pdaf_vdev *pdaf_vdev = dev->pdaf_vdev;
u32 val, size = 0, div = dev->unite_div;
if (dev->isp_sdev.in_fmt.fmt_type == FMT_YUV)
@@ -506,7 +502,7 @@ void rkisp_stats_first_ddr_config_v39(struct rkisp_isp_stats_vdev *stats_vdev)
val = ISP39_W3A_EN | ISP39_W3A_FORCE_UPD;
if (!dev->is_aiisp_en || dev->is_aiisp_sync)
val |= ISP39_W3A_AUTO_CLR_EN;
if (pdaf_vdev->streaming) {
if (pdaf_vdev && pdaf_vdev->streaming) {
val |= ISP39_W3A_PDAF_EN;
rkisp_pdaf_update_buf(dev);
if (pdaf_vdev->next_buf) {
@@ -522,11 +518,12 @@ void rkisp_stats_first_ddr_config_v39(struct rkisp_isp_stats_vdev *stats_vdev)
}
}
void rkisp_stats_next_ddr_config_v39(struct rkisp_isp_stats_vdev *stats_vdev)
static void
rkisp_stats_next_ddr_config_v39(struct rkisp_isp_stats_vdev *stats_vdev)
{
struct rkisp_device *dev = stats_vdev->dev;
struct rkisp_hw_dev *hw = dev->hw_dev;
struct rkisp_pdaf_vdev *pdaf_vdev = &dev->pdaf_vdev;
struct rkisp_pdaf_vdev *pdaf_vdev = dev->pdaf_vdev;
if (!stats_vdev->streamon || dev->isp_sdev.in_fmt.fmt_type == FMT_YUV)
return;
@@ -534,11 +531,18 @@ void rkisp_stats_next_ddr_config_v39(struct rkisp_isp_stats_vdev *stats_vdev)
if (hw->is_single) {
if (!dev->is_aiisp_en || dev->is_aiisp_sync)
rkisp_stats_update_buf(stats_vdev);
if (pdaf_vdev->streaming)
if (pdaf_vdev && pdaf_vdev->streaming)
rkisp_pdaf_update_buf(dev);
}
}
static struct rkisp_isp_stats_ops rkisp_isp_stats_ops_tbl = {
.isr_hdl = rkisp_stats_isr_v39,
.get_stat_size = rkisp_get_stat_size_v39,
.first_ddr_cfg = rkisp_stats_first_ddr_config_v39,
.next_ddr_cfg = rkisp_stats_next_ddr_config_v39,
};
void rkisp_init_stats_vdev_v39(struct rkisp_isp_stats_vdev *stats_vdev)
{
stats_vdev->ops = &rkisp_isp_stats_ops_tbl;

4
drivers/media/platform/rockchip/isp/isp_stats_v39.h
View File

@@ -14,13 +14,9 @@
struct rkisp_isp_stats_vdev;
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V39)
void rkisp_stats_first_ddr_config_v39(struct rkisp_isp_stats_vdev *stats_vdev);
void rkisp_stats_next_ddr_config_v39(struct rkisp_isp_stats_vdev *stats_vdev);
void rkisp_init_stats_vdev_v39(struct rkisp_isp_stats_vdev *stats_vdev);
void rkisp_uninit_stats_vdev_v39(struct rkisp_isp_stats_vdev *stats_vdev);
#else
static inline void rkisp_stats_first_ddr_config_v39(struct rkisp_isp_stats_vdev *stats_vdev) {}
static inline void rkisp_stats_next_ddr_config_v39(struct rkisp_isp_stats_vdev *stats_vdev) {}
static inline void rkisp_init_stats_vdev_v39(struct rkisp_isp_stats_vdev *stats_vdev) {}
static inline void rkisp_uninit_stats_vdev_v39(struct rkisp_isp_stats_vdev *stats_vdev) {}
#endif

18
drivers/media/platform/rockchip/isp/isp_stats_v3x.c
View File

@@ -1171,14 +1171,8 @@ rkisp_get_stat_size_v3x(struct rkisp_isp_stats_vdev *stats_vdev,
stats_vdev->vdev_fmt.fmt.meta.buffersize = sizes[0];
}
static struct rkisp_isp_stats_ops rkisp_isp_stats_ops_tbl = {
.isr_hdl = rkisp_stats_isr_v3x,
.send_meas = rkisp_stats_send_meas_v3x,
.rdbk_enable = rkisp_stats_rdbk_enable_v3x,
.get_stat_size = rkisp_get_stat_size_v3x,
};
void rkisp_stats_first_ddr_config_v3x(struct rkisp_isp_stats_vdev *stats_vdev)
static void
rkisp_stats_first_ddr_config_v3x(struct rkisp_isp_stats_vdev *stats_vdev)
{
struct rkisp_device *dev = stats_vdev->dev;
int i, mult = dev->unite_div;
@@ -1217,6 +1211,14 @@ err:
dev_err(dev->dev, "alloc stats ddr buf fail\n");
}
static struct rkisp_isp_stats_ops rkisp_isp_stats_ops_tbl = {
.isr_hdl = rkisp_stats_isr_v3x,
.send_meas = rkisp_stats_send_meas_v3x,
.rdbk_enable = rkisp_stats_rdbk_enable_v3x,
.get_stat_size = rkisp_get_stat_size_v3x,
.first_ddr_cfg = rkisp_stats_first_ddr_config_v3x,
};
void rkisp_init_stats_vdev_v3x(struct rkisp_isp_stats_vdev *stats_vdev)
{
stats_vdev->ops = &rkisp_isp_stats_ops_tbl;

2
drivers/media/platform/rockchip/isp/isp_stats_v3x.h
View File

@@ -40,11 +40,9 @@ struct rkisp_stats_ops_v3x {
};
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V30)
void rkisp_stats_first_ddr_config_v3x(struct rkisp_isp_stats_vdev *stats_vdev);
void rkisp_init_stats_vdev_v3x(struct rkisp_isp_stats_vdev *stats_vdev);
void rkisp_uninit_stats_vdev_v3x(struct rkisp_isp_stats_vdev *stats_vdev);
#else
static inline void rkisp_stats_first_ddr_config_v3x(struct rkisp_isp_stats_vdev *stats_vdev) {}
static inline void rkisp_init_stats_vdev_v3x(struct rkisp_isp_stats_vdev *stats_vdev) {}
static inline void rkisp_uninit_stats_vdev_v3x(struct rkisp_isp_stats_vdev *stats_vdev) {}
#endif

161
drivers/media/platform/rockchip/isp/procfs.c
View File

@@ -13,6 +13,7 @@
#include "isp_params_v3x.h"
#include "isp_params_v32.h"
#include "isp_params_v33.h"
#include "isp_params_v35.h"
#include "isp_params_v39.h"
#ifdef CONFIG_PROC_FS
@@ -1134,6 +1135,162 @@ static void isp33_show(struct rkisp_device *dev, struct seq_file *p)
!!(val & BIT(3)), !!(val & BIT(2)), !!(val & BIT(1)), !!(val & BIT(0)));
}
static void isp35_show(struct rkisp_device *dev, struct seq_file *p)
{
struct rkisp_isp_params_val_v35 *priv = dev->params_vdev.priv_val;
u32 full_range_flg = CIF_ISP_CTRL_ISP_CSM_Y_FULL_ENA | CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA;
static const char * const effect[] = { "OFF", "BLACKWHITE" };
u32 val, tmp;
val = rkisp_read(dev, ISP3X_SWS_CFG, false);
tmp = rkisp_read(dev, ISP3X_SWS_CFG, true);
seq_printf(p, "%-10s %s wrap:%d isp2enc(path_en:%d pipe_en:%d hold:%d)\n", "ISP2ENC",
dev->cap_dev.wrap_line ? "online" : "offline",
dev->cap_dev.wrap_line,
!!(val & BIT(5)), !!(val & BIT(1)), !!(tmp & BIT(31)));
val = rkisp_read(dev, ISP3X_GIC_CONTROL, false);
seq_printf(p, "%-10s %s(0x%x) bypass:%d\n", "GIC", (val & 1) ? "ON" : "OFF",
val, !!(val & BIT(1)));
val = rkisp_read(dev, ISP3X_CAC_CTRL, false);
seq_printf(p, "%-10s %s(0x%x) bypass:%d\n", "CAC", (val & (BIT(0) | BIT(31))) ? "ON" : "OFF",
val, !!(val & (BIT(1) | BIT(30))));
val = rkisp_read(dev, ISP3X_ISP_CTRL0, false);
seq_printf(p, "%-10s %s(0x%x) (gain0:0x%08x 0x%08x gain1:0x%x 0x%x)\n", "AWBGAIN",
(val & BIT(7)) ? "ON" : "OFF", val,
rkisp_read(dev, ISP3X_ISP_AWB_GAIN0_G, false),
rkisp_read(dev, ISP3X_ISP_AWB_GAIN0_RB, false),
rkisp_read(dev, ISP32_ISP_AWB1_GAIN_G, false),
rkisp_read(dev, ISP32_ISP_AWB1_GAIN_RB, false));
val = rkisp_read(dev, ISP3X_DPCC0_MODE, false);
seq_printf(p, "%-10s %s(0x%x)\n", "DPCC0", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_DPCC1_MODE, false);
seq_printf(p, "%-10s %s(0x%x)\n", "DPCC1", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_BLS_CTRL, false);
seq_printf(p, "%-10s %s(0x%x)\n", "BLS", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_LSC_CTRL, false);
seq_printf(p, "%-10s %s(0x%x)\n", "LSC", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_DEBAYER_CONTROL, false);
seq_printf(p, "%-10s %s(0x%x) bypass:%d\n", "DEBAYER", (val & (BIT(0) | BIT(29))) ? "ON" : "OFF",
val, !!(val & (BIT(1) | BIT(27))));
val = rkisp_read(dev, ISP3X_CCM_CTRL, false);
seq_printf(p, "%-10s %s(0x%x)\n", "CCM", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_GAMMA_OUT_CTRL, false);
seq_printf(p, "%-10s %s(0x%x)\n", "GAMMA_OUT", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_CPROC_CTRL, false);
seq_printf(p, "%-10s %s(0x%x)\n", "CPROC", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_IMG_EFF_CTRL, false);
seq_printf(p, "%-10s %s(0x%x) (effect: %s)\n", "IE",
(val & 1) ? "ON" : "OFF", val, effect[!!val]);
val = rkisp_read(dev, ISP3X_DRC_CTRL0, false);
seq_printf(p, "%-10s %s(0x%x) bypass:%d lp_en:%d\n", "DRC", (val & 1) ? "ON" : "OFF",
val, !!(val & BIT(1)), !!(val & BIT(4)));
val = rkisp_read(dev, ISP3X_HDRMGE_CTRL, false);
seq_printf(p, "%-10s %s(0x%x) wrap:%d\n", "HDRMGE", (val & 1) ? "ON" : "OFF",
val, dev->hdr_wrap_line);
val = rkisp_read(dev, ISP33_BAY3D_CTRL0, false);
tmp = rkisp_read(dev, ISP33_BAY3D_CTRL2, false);
seq_printf(p, "%-10s %s(0x%x) bypass:%d iir_rw_fmt:%d b3dldch:0x%x b3dldcv:0x%x\n"
"\t lp_en(me_off:%d gic:%d bf:%d avg:%d) size(iir:%d ds:%d wgt:%d)\n",
"BAY3D", (val & 1) ? "ON" : "OFF", val, !!(val & BIT(1)), (val >> 13) & 0x7,
rkisp_read(dev, ISP35_B3DLDC_ADR_STS, false),
rkisp_read(dev, ISP35_B3DLDC_CTRL, false),
!(val & BIT(8)), !!(tmp & BIT(20)), !!(tmp & BIT(21)), !!(tmp & BIT(22)),
priv->buf_3dnr_iir.size, priv->buf_3dnr_ds.size, priv->buf_3dnr_wgt.size);
val = rkisp_read(dev, ISP3X_YNR_GLOBAL_CTRL, false);
seq_printf(p, "%-10s %s(0x%x) bypass(hi:%d mi:%d lo:%d) lp_en:%d\n", "YNR",
(val & 1) ? "ON" : "OFF", val,
!!(val & BIT(1)), !!(val & BIT(2)), !!(val & BIT(3)), !!(val & BIT(6)));
val = rkisp_read(dev, ISP3X_CNR_CTRL, false);
seq_printf(p, "%-10s %s(0x%x)\n", "CNR", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_SHARP_EN, false);
seq_printf(p, "%-10s %s(0x%x) lp_en:%d\n", "SHARP",
(val & 1) ? "ON" : "OFF", val, !!(val & BIT(10)));
val = rkisp_read(dev, ISP33_ENH_CTRL, false);
seq_printf(p, "%-10s %s(0x%x) bypass:%d lp_en:%d\n", "ENH", (val & 1) ? "ON" : "OFF",
val, !!(val & BIT(1)), !!(val & BIT(2)));
val = rkisp_read(dev, ISP33_HIST_CTRL, false);
seq_printf(p, "%-10s %s(0x%x) bypass:%d\n", "HIST", (val & 1) ? "ON" : "OFF",
val, !!(val & BIT(1)));
val = rkisp_read(dev, ISP33_HSV_CTRL, false);
seq_printf(p, "%-10s %s(0x%x)\n", "HSV", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_LDCH_STS, false);
seq_printf(p, "%-10s %s(0x%x)\n", "LDCH", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_ISP_CTRL0, false);
tmp = rkisp_read(dev, ISP3X_ISP_CC_COEFF_0, false);
seq_printf(p, "%-10s %s(0x%x), y_offs:0x%x c_offs:0x%x\n"
"\t coeff Y:0x%x 0x%x 0x%x CB:0x%x 0x%x 0x%x CR:0x%x 0x%x 0x%x\n",
"CSM", (val & full_range_flg) ? "FULL" : "LIMIT", val,
(tmp >> 24) & 0x3f,
(tmp >> 16) & 0xff ? (tmp >> 16) & 0xff : 128,
tmp & 0x1ff,
rkisp_read(dev, ISP3X_ISP_CC_COEFF_1, false),
rkisp_read(dev, ISP3X_ISP_CC_COEFF_2, false),
rkisp_read(dev, ISP3X_ISP_CC_COEFF_3, false),
rkisp_read(dev, ISP3X_ISP_CC_COEFF_4, false),
rkisp_read(dev, ISP3X_ISP_CC_COEFF_5, false),
rkisp_read(dev, ISP3X_ISP_CC_COEFF_6, false),
rkisp_read(dev, ISP3X_ISP_CC_COEFF_7, false),
rkisp_read(dev, ISP3X_ISP_CC_COEFF_8, false));
val = rkisp_read(dev, ISP3X_GAIN_CTRL, false);
seq_printf(p, "%-10s %s(0x%x)\n", "GAIN", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP32_BLS_ISP_OB_PREDGAIN, false);
tmp = rkisp_read(dev, ISP32_BLS_ISP_OB_OFFSET, false);
seq_printf(p, "%-10s %s pregdain:0x%x offset:0x%x offset1:%d max:0x%x\n",
"OB", val ? "ON" : "OFF", val, tmp & 0x1ff, (tmp >> 16) & 0x1ff,
rkisp_read(dev, ISP32_BLS_ISP_OB_MAX, false));
val = rkisp_read(dev, ISP3X_RAWAE_LITE_CTRL, false);
seq_printf(p, "%-10s %s(0x%x)\n", "RAWAE0", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_RAWAE_BIG1_BASE, false);
seq_printf(p, "%-10s %s(0x%x)\n", "RAWAE3", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_RAWHIST_LITE_CTRL, false);
seq_printf(p, "%-10s %s(0x%x)\n", "RAWHIST0", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_RAWHIST_BIG1_BASE, false);
seq_printf(p, "%-10s %s(0x%x)\n", "RAWHIST3", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_RAWAF_CTRL, false);
seq_printf(p, "%-10s %s(0x%x)\n", "RAWAF", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_RAWAWB_CTRL, false);
seq_printf(p, "%-10s %s(0x%x)\n", "RAWAWB", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP35_AIAWB_CTRL0, false);
seq_printf(p, "%-10s %s(0x%x) idx:%d cnt:%d\n", "AIAWB", (val & 1) ? "ON" : "OFF",
val, priv->buf_aiawb_cnt, priv->buf_aiawb_idx);
val = rkisp_read(dev, ISP35_AWBSYNC_CTRL, false);
seq_printf(p, "%-10s %s(0x%x)\n", "AWBSYNC", (val & 1) ? "ON" : "OFF", val);
val = rkisp_read(dev, ISP3X_ISP_DEBUG1, true);
seq_printf(p, "%-10s space full status group(0x%x) isp2enc_cnt:%d\n"
"\t ibuf2:0x%x ibuf1:0x%x ibuf0:0x%x\n"
"\t outfifo:0x%x lafifo:0x%x\n",
"DEBUG1", val, val & 0xff,
val >> 28, (val >> 24) & 0xf, (val >> 20) & 0xf,
(val >> 12) & 0xf, (val >> 8) & 0xf);
val = rkisp_read(dev, ISP3X_ISP_DEBUG2, true);
seq_printf(p, "%-10s 0x%x\n"
"\t bay3d_fifo_full iir:%d cur:%d\n"
"\t module outform vertical counter:%d, out frame counter:%d\n"
"\t isp output line counter:%d\n",
"DEBUG2", val, !!(val & BIT(31)), !!(val & BIT(30)),
(val >> 16) & 0x3fff, (val >> 14) & 0x3, val & 0x3fff);
val = rkisp_read(dev, ISP3X_ISP_DEBUG3, true);
seq_printf(p, "%-10s isp pipeline group (0x%x)\n"
"\t mge(%d %d) rawnr(%d %d) bay3d(%d %d) tmo(%d %d)\n"
"\t gic(%d %d) dbr(%d %d) debayer(%d %d) dhaz(%d %d)\n"
"\t lut3d(%d %d) ldch(%d %d) ynr(%d %d) shp(%d %d)\n"
"\t cgc(%d %d) cac(%d %d) isp_out(%d %d) isp_in(%d %d)\n",
"DEBUG3", val,
!!(val & BIT(31)), !!(val & BIT(30)), !!(val & BIT(29)), !!(val & BIT(28)),
!!(val & BIT(27)), !!(val & BIT(26)), !!(val & BIT(25)), !!(val & BIT(24)),
!!(val & BIT(23)), !!(val & BIT(22)), !!(val & BIT(21)), !!(val & BIT(20)),
!!(val & BIT(19)), !!(val & BIT(18)), !!(val & BIT(17)), !!(val & BIT(16)),
!!(val & BIT(15)), !!(val & BIT(14)), !!(val & BIT(13)), !!(val & BIT(12)),
!!(val & BIT(11)), !!(val & BIT(10)), !!(val & BIT(9)), !!(val & BIT(8)),
!!(val & BIT(7)), !!(val & BIT(6)), !!(val & BIT(5)), !!(val & BIT(4)),
!!(val & BIT(3)), !!(val & BIT(2)), !!(val & BIT(1)), !!(val & BIT(0)));
val = rkisp_read(dev, ISP32_ISP_DEBUG4, true);
seq_printf(p, "%-10s isp pipeline group (0x%x)\n"
"\t expd(%d %d) ynr(%d %d)\n",
"DEBUG4", val,
!!(val & BIT(3)), !!(val & BIT(2)), !!(val & BIT(1)), !!(val & BIT(0)));
}
static int isp_show(struct seq_file *p, void *v)
{
struct rkisp_device *dev = p->private;
@@ -1264,6 +1421,10 @@ static int isp_show(struct seq_file *p, void *v)
if (IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V33))
isp33_show(dev, p);
break;
case ISP_V35:
if (IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V35))
isp35_show(dev, p);
break;
default:
break;
}

5
drivers/media/platform/rockchip/isp/regs.c
View File

@@ -482,7 +482,7 @@ void rkisp_config_rsz(struct rkisp_stream *stream, struct v4l2_rect *in_y,
struct rkisp_device *dev = stream->ispdev;
int i = 0;
if (dev->isp_ver == ISP_V39 || dev->isp_ver == ISP_V33 ||
if (dev->isp_ver >= ISP_V33 ||
(dev->isp_ver == ISP_V32_L && stream->id == RKISP_STREAM_SP)) {
set_bilinear_scale(stream, in_y, in_c, out_y, out_c, async);
return;
@@ -508,8 +508,7 @@ void rkisp_config_rsz(struct rkisp_stream *stream, struct v4l2_rect *in_y,
void rkisp_disable_rsz(struct rkisp_stream *stream, bool async)
{
rkisp_unite_write(stream->ispdev, stream->config->rsz.ctrl, 0, false);
if (stream->ispdev->isp_ver == ISP_V39 ||
stream->ispdev->isp_ver == ISP_V33 ||
if (stream->ispdev->isp_ver >= ISP_V33 ||
(stream->ispdev->isp_ver == ISP_V32_L && stream->id == RKISP_STREAM_SP))
return;
update_rsz_shadow(stream, async);

169
drivers/media/platform/rockchip/isp/regs_v3x.h
View File

@@ -532,6 +532,22 @@
#define ISP39_LDCV_OUT_SIZE (ISP39_LDCV_BASE + 0x0003c)
#define ISP39_LDCV_WR_C_ADDR (ISP39_LDCV_BASE + 0x00040)
#define ISP35_AI_BASE 0x00001200
#define ISP35_AI_CTRL (ISP35_AI_BASE + 0x00000)
#define ISP35_AI_SIGMA_Y0 (ISP35_AI_BASE + 0x00010)
#define ISP35_AI_SIGMA_Y16 (ISP35_AI_BASE + 0x00050)
#define ISP35_AI_PRE_NL_WR_BASE (ISP35_AI_BASE + 0x00054)
#define ISP35_AI_PRE_NL_WR_STRIDE (ISP35_AI_BASE + 0x00058)
#define ISP35_AI_PRE_GAIN_WR_BASE (ISP35_AI_BASE + 0x0005c)
#define ISP35_AI_PRE_GAIN_WR_STRIDE (ISP35_AI_BASE + 0x00060)
#define ISP35_AI_PRE_NL_PRE (ISP35_AI_BASE + 0x00064)
#define ISP35_AI_PRE_GAIN_PARA (ISP35_AI_BASE + 0x00068)
#define ISP35_AI_PRE_SIGMA_CURVE0 (ISP35_AI_BASE + 0x0006c)
#define ISP35_AI_PRE_SIGMA_CURVE10 (ISP35_AI_BASE + 0x00094)
#define ISP35_AI_PRE_NOISE0 (ISP35_AI_BASE + 0x00098)
#define ISP35_AI_PRE_NOISE1 (ISP35_AI_BASE + 0x0009c)
#define ISP35_AI_PRE_NOISE2 (ISP35_AI_BASE + 0x000A0)
#define ISP3X_MI_BASE 0x00001400
#define ISP3X_MI_WR_CTRL (ISP3X_MI_BASE + 0x00000)
#define ISP3X_MI_WR_INIT (ISP3X_MI_BASE + 0x00004)
@@ -760,6 +776,16 @@
#define ISP32L_FRM_BUF_WR_BASE (ISP3X_MI_BASE + 0x00650)
#define ISP32L_FRM_BUF_WR_SIZE (ISP3X_MI_BASE + 0x00654)
#define ISP32L_FRM_BUF_RD_BASE (ISP3X_MI_BASE + 0x00658)
#define ISP35_B3DLDCH_RD_BASE (ISP3X_MI_BASE + 0x00600)
#define ISP35_B3DLDCH_RD_LENGTH (ISP3X_MI_BASE + 0x00604)
#define ISP35_B3DLDCH_RD_HWSIZE (ISP3X_MI_BASE + 0x00608)
#define ISP35_B3DLDCH_RD_VSIZE (ISP3X_MI_BASE + 0x0060c)
#define ISP35_B3DLDCH_RD_BASE_SHD (ISP3X_MI_BASE + 0x00620)
#define ISP35_B3DLDCV_RD_BASE_SHD (ISP3X_MI_BASE + 0x00628)
#define ISP35_B3DLDCV_RD_BASE (ISP3X_MI_BASE + 0x00630)
#define ISP35_B3DLDCV_RD_LENGTH (ISP3X_MI_BASE + 0x00634)
#define ISP35_B3DLDCV_RD_HWSIZE (ISP3X_MI_BASE + 0x00638)
#define ISP35_B3DLDCV_RD_VSIZE (ISP3X_MI_BASE + 0x0063C)
#define ISP3X_MPFBC_BASE 0x000018C0
#define ISP3X_MPFBC_CTRL (ISP3X_MPFBC_BASE + 0x00000)
@@ -1073,6 +1099,10 @@
#define ISP33_YNR_LO_TEXT_THRED (ISP3X_YNR_BASE + 0x000ec)
#define ISP33_YNR_FUSION_WEIT_ADJ_0_3 (ISP3X_YNR_BASE + 0x000f0)
#define ISP33_YNR_FUSION_WEIT_ADJ_8 (ISP3X_YNR_BASE + 0x000f8)
#define ISP35_YNR_MI_TEX2WGT_SCALE_0_1_2 (ISP3X_YNR_BASE + 0x00088)
#define ISP35_YNR_LO_TEX2WGT_SCALE_0_1_2 (ISP3X_YNR_BASE + 0x00094)
#define ISP35_YNR_MI_GAUS_COE1 (ISP3X_YNR_BASE + 0x000d0)
#define ISP35_YNR_DSIIR_COE (ISP3X_YNR_BASE + 0x000dc)
#define ISP3X_CNR_BASE 0x00002800
#define ISP3X_CNR_CTRL (ISP3X_CNR_BASE + 0x00000)
@@ -1116,6 +1146,14 @@
#define ISP39_CNR_GAUS_Y_SIGMAR1 (ISP3X_CNR_BASE + 0x00064)
#define ISP39_CNR_GAUS_Y_SIGMAR2 (ISP3X_CNR_BASE + 0x00068)
#define ISP39_CNR_GAUS_Y_SIGMAR3 (ISP3X_CNR_BASE + 0x0006c)
#define ISP35_CNR_IIR_SIGMAR0 (ISP3X_CNR_BASE + 0x00070)
#define ISP35_CNR_IIR_SIGMAR3 (ISP3X_CNR_BASE + 0x0007c)
#define ISP35_CNR_HSV_CURVE0 (ISP3X_CNR_BASE + 0x00080)
#define ISP35_CNR_HSV_CURVE2 (ISP3X_CNR_BASE + 0x00088)
#define ISP35_CNR_SAT_CURVE0 (ISP3X_CNR_BASE + 0x0008c)
#define ISP35_CNR_SAT_CURVE2 (ISP3X_CNR_BASE + 0x00094)
#define ISP35_CNR_GAIN_ADJ_CURVE0 (ISP3X_CNR_BASE + 0x00098)
#define ISP35_CNR_GAIN_ADJ_CURVE2 (ISP3X_CNR_BASE + 0x000a0)
#define ISP3X_SHARP_BASE 0x00002900
#define ISP3X_SHARP_EN (ISP3X_SHARP_BASE + 0x00000)
@@ -1259,6 +1297,16 @@
#define ISP33_SHARP_NOISE_CURVE0 (ISP3X_SHARP_BASE + 0x00170)
#define ISP33_SHARP_NOISE_CURVE8 (ISP3X_SHARP_BASE + 0x00190)
#define ISP33_SHARP_NOISE_CLIP (ISP3X_SHARP_BASE + 0x00194)
#define ISP35_SHARP_TEX2DETAIL_STRG0 (ISP3X_SHARP_BASE + 0x0013c)
#define ISP35_SHARP_TEX2DETAIL_STRG2 (ISP3X_SHARP_BASE + 0x00144)
#define ISP35_SHARP_TEX2MFDETAIL_STRG0 (ISP3X_SHARP_BASE + 0x0015c)
#define ISP35_SHARP_TEX2MFDETAIL_STRG2 (ISP3X_SHARP_BASE + 0x00164)
#define ISP35_SHARP_EDGEWGTFLT_KERNEL (ISP3X_SHARP_BASE + 0x00198)
#define ISP35_SHARP_EDGE_GLOBAL_CLIP (ISP3X_SHARP_BASE + 0x001a0)
#define ISP35_SHARP_MFDETAIL (ISP3X_SHARP_BASE + 0x001a4)
#define ISP35_SHARP_MFDETAIL_CLIP (ISP3X_SHARP_BASE + 0x001a8)
#define ISP35_SHARP_SATURATION_STRG0 (ISP3X_SHARP_BASE + 0x001ac)
#define ISP35_SHARP_SATURATION_STRG2 (ISP3X_SHARP_BASE + 0x001b4)
#define ISP33_BAY3D_BASE 0x00002B00
#define ISP33_BAY3D_CTRL0 (ISP33_BAY3D_BASE + 0x00000)
@@ -1323,6 +1371,13 @@
#define ISP33_BAY3D_MIDBIG2 (ISP33_BAY3D_BASE + 0x00288)
#define ISP33_BAY3D_TNRSUM (ISP33_BAY3D_BASE + 0x002d4)
#define ISP33_BAY3D_TNRYO0 (ISP33_BAY3D_BASE + 0x002d8)
#define ISP35_BAY3D_PREHI_SIGSCL (ISP33_BAY3D_BASE + 0x00058)
#define ISP35_BAY3D_PREHI_SIGOF (ISP33_BAY3D_BASE + 0x00068)
#define ISP35_BAY3D_LOCOEF0 (ISP33_BAY3D_BASE + 0x001f0)
#define ISP35_BAY3D_LOCOEF1 (ISP33_BAY3D_BASE + 0x001f4)
#define ISP35_BAY3D_DPC0 (ISP33_BAY3D_BASE + 0x001f8)
#define ISP35_BAY3D_DPC1 (ISP33_BAY3D_BASE + 0x001fc)
#define ISP35_BAY3D_MONROFF (ISP33_BAY3D_BASE + 0x0028c)
#define ISP3X_BAY3D_BASE 0x00002C00
#define ISP3X_BAY3D_CTRL (ISP3X_BAY3D_BASE + 0x00000)
@@ -1594,6 +1649,8 @@
#define ISP32_BLS_ISP_OB_OFFSET (ISP3X_BLS_BASE + 0x00068)
#define ISP32_BLS_ISP_OB_PREDGAIN (ISP3X_BLS_BASE + 0x0006c)
#define ISP32_BLS_ISP_OB_MAX (ISP3X_BLS_BASE + 0x00070)
#define ISP35_BLS3_AB_FIXED (ISP3X_BLS_BASE + 0x00074)
#define ISP35_BLS3_CD_FIXED (ISP3X_BLS_BASE + 0x00078)
#define ISP39_EXPD_BASE 0x00003100
#define ISP39_EXPD_K15 (ISP39_EXPD_BASE + 0x00000)
@@ -1902,6 +1959,8 @@
#define ISP3X_HDRMGE_OVER_Y15 (ISP3X_HDRMGE_BASE + 0x000ac)
#define ISP3X_HDRMGE_OVER_Y16 (ISP3X_HDRMGE_BASE + 0x000b0)
#define ISP32_HDRMGE_EACH_GAIN (ISP3X_HDRMGE_BASE + 0x000b4)
#define ISP35_HDRMGE_FORCE_LONG0 (ISP3X_HDRMGE_BASE + 0x000b8)
#define ISP35_HDRMGE_FORCE_LONG1 (ISP3X_HDRMGE_BASE + 0x000bc)
#define ISP3X_DRC_BASE 0x00003900
#define ISP3X_DRC_CTRL0 (ISP3X_DRC_BASE + 0x00000)
@@ -1956,6 +2015,7 @@
#define ISP39_DRC_SFTHD_Y6 (ISP3X_DRC_BASE + 0x000a8)
#define ISP39_DRC_SFTHD_Y7 (ISP3X_DRC_BASE + 0x000ac)
#define ISP39_DRC_SFTHD_Y8 (ISP3X_DRC_BASE + 0x000b0)
#define ISP35_DRC_LUMA_MIX (ISP3X_DRC_BASE + 0x000b4)
#define ISP3X_BAYNR_BASE 0x00003A00
#define ISP3X_BAYNR_CTRL (ISP3X_BAYNR_BASE + 0x00000)
@@ -2027,6 +2087,11 @@
#define ISP32_LDCH_BIC_TABLE7 (ISP3X_LDCH_BASE + 0x00020)
#define ISP32_LDCH_BIC_TABLE8 (ISP3X_LDCH_BASE + 0x00024)
#define ISP39_LDCH_OUT_SIZE (ISP3X_LDCH_BASE + 0x00028)
#define ISP35_B3DLDC_CTRL (ISP3X_LDCH_BASE + 0x00080)
#define ISP35_B3DLDC_WR_ADDR (ISP3X_LDCH_BASE + 0x000a8)
#define ISP35_B3DLDC_WR_STRIDE (ISP3X_LDCH_BASE + 0x000ac)
#define ISP35_B3DLDC_ADR_STS (ISP3X_LDCH_BASE + 0x000e0)
#define ISP35_B3DLDC_EXTBOUND1 (ISP3X_LDCH_BASE + 0x000e8)
#define ISP3X_DHAZ_BASE 0x00003C00
#define ISP3X_DHAZ_CTRL (ISP3X_DHAZ_BASE + 0x00000)
@@ -2220,6 +2285,36 @@
#define ISP33_HSV_UPDATE (ISP33_HSV_BASE + 0x00004)
#define ISP33_HSV_1DLUT (ISP33_HSV_BASE + 0x00008)
#define ISP33_HSV_2DLUT (ISP33_HSV_BASE + 0x0000c)
#define ISP35_HSV_MODE_CTRL (ISP33_HSV_BASE + 0x00004)
#define ISP35_HSV_1DLUT (ISP33_HSV_BASE + 0x0000c)
#define ISP35_HSV_2DLUT0 (ISP33_HSV_BASE + 0x00010)
#define ISP35_HSV_2DLUT1 (ISP33_HSV_BASE + 0x00014)
#define ISP35_HSV_2DLUT2 (ISP33_HSV_BASE + 0x00018)
#define ISP35_AWBSYNC_BASE 0x00003E80
#define ISP35_AWBSYNC_CTRL (ISP35_AWBSYNC_BASE + 0x00000)
#define ISP35_AWBSYNC_SCL (ISP35_AWBSYNC_BASE + 0x00004)
#define ISP35_AWBSYNC_SUMVAL_MIN (ISP35_AWBSYNC_BASE + 0x00008)
#define ISP35_AWBSYNC_SUMVAL_MAX (ISP35_AWBSYNC_BASE + 0x0000C)
#define ISP35_AWBSYNC_WIN0_OFFS (ISP35_AWBSYNC_BASE + 0x00010)
#define ISP35_AWBSYNC_WIN0_RD_COOR (ISP35_AWBSYNC_BASE + 0x00014)
#define ISP35_AWBSYNC_WIN1_OFFS (ISP35_AWBSYNC_BASE + 0x00018)
#define ISP35_AWBSYNC_WIN1_RD_COOR (ISP35_AWBSYNC_BASE + 0x0001C)
#define ISP35_AWBSYNC_WIN2_OFFS (ISP35_AWBSYNC_BASE + 0x00020)
#define ISP35_AWBSYNC_WIN2_RD_COOR (ISP35_AWBSYNC_BASE + 0x00024)
#define ISP35_AWBSYNC_WIN0_SUMR (ISP35_AWBSYNC_BASE + 0x00030)
#define ISP35_AWBSYNC_WIN0_SUMG (ISP35_AWBSYNC_BASE + 0x00034)
#define ISP35_AWBSYNC_WIN0_SUMB (ISP35_AWBSYNC_BASE + 0x00038)
#define ISP35_AWBSYNC_WIN0_SUMP (ISP35_AWBSYNC_BASE + 0x0003C)
#define ISP35_AWBSYNC_WIN1_SUMR (ISP35_AWBSYNC_BASE + 0x00040)
#define ISP35_AWBSYNC_WIN1_SUMG (ISP35_AWBSYNC_BASE + 0x00044)
#define ISP35_AWBSYNC_WIN1_SUMB (ISP35_AWBSYNC_BASE + 0x00048)
#define ISP35_AWBSYNC_WIN1_SUMP (ISP35_AWBSYNC_BASE + 0x0004C)
#define ISP35_AWBSYNC_WIN2_SUMR (ISP35_AWBSYNC_BASE + 0x00050)
#define ISP35_AWBSYNC_WIN2_SUMG (ISP35_AWBSYNC_BASE + 0x00054)
#define ISP35_AWBSYNC_WIN2_SUMB (ISP35_AWBSYNC_BASE + 0x00058)
#define ISP35_AWBSYNC_WIN2_SUMP (ISP35_AWBSYNC_BASE + 0x0005C)
#define ISP35_AWBSYNC_DBG0 (ISP35_AWBSYNC_BASE + 0x00060)
#define ISP3X_GAIN_BASE 0x00003F00
#define ISP3X_GAIN_CTRL (ISP3X_GAIN_BASE + 0x00000)
@@ -2666,6 +2761,22 @@
#define ISP33_RAWAWB_CCM_COEFF0_B (ISP3X_RAWAWB_BASE + 0x01d0)
#define ISP33_RAWAWB_CCM_COEFF1_B (ISP3X_RAWAWB_BASE + 0x01d4)
#define ISP35_AIAWB_BASE 0x00005a00
#define ISP35_AIAWB_CTRL0 (ISP35_AIAWB_BASE + 0x0000)
#define ISP35_AIAWB_CTRL1 (ISP35_AIAWB_BASE + 0x0004)
#define ISP35_AIAWB_WIN_OFFS (ISP35_AIAWB_BASE + 0x0008)
#define ISP35_AIAWB_WIN_SIZE (ISP35_AIAWB_BASE + 0x000c)
#define ISP35_AIAWB_FLT_COE0 (ISP35_AIAWB_BASE + 0x0010)
#define ISP35_AIAWB_FLT_COE1 (ISP35_AIAWB_BASE + 0x0014)
#define ISP35_AIAWB_WBGAIN_INV0 (ISP35_AIAWB_BASE + 0x0018)
#define ISP35_AIAWB_WBGAIN_INV1 (ISP35_AIAWB_BASE + 0x001c)
#define ISP35_AIAWB_MATRIX_SCALE (ISP35_AIAWB_BASE + 0x0020)
#define ISP35_AIAWB_MATRIX_ROT0 (ISP35_AIAWB_BASE + 0x0024)
#define ISP35_AIAWB_MATRIX_ROT1 (ISP35_AIAWB_BASE + 0x0028)
#define ISP35_AIAWB_WR_BASE (ISP35_AIAWB_BASE + 0x0030)
#define ISP35_AIAWB_WR_BASE_SHD (ISP35_AIAWB_BASE + 0x0034)
#define ISP35_AIAWB_WR_BASE_VIR (ISP35_AIAWB_BASE + 0x0038)
/* VI_ISP_PATH */
#define ISP3X_RAWAE3_SEL(x) (((x) & 3) << 16)
#define ISP3X_RAWAF_SEL(x) (((x) & 3) << 18)
@@ -2712,8 +2823,11 @@
#define ISP32_MIR_ENABLE BIT(5)
#define ISP3X_SW_CGC_YUV_LIMIT BIT(28)
#define ISP3X_SW_CGC_RATIO_EN BIT(29)
#define ISP35_ISP_CFG_UPD_FE BIT(31)
/* ISP CTRL1 */
#define ISP35_BAYER_UPD_FE_EN BIT(0)
#define ISP35_BAYER_PAT_FE(x) (((x) & 0x3) << 1)
#define ISP39_YUVME_FST_FRAME BIT(18)
#define ISP32_SHP_FST_FRAME BIT(19)
#define ISP3X_YNR_FST_FRAME BIT(23)
@@ -2781,11 +2895,15 @@
#define ISP3X_3A_RAWHIST_CH2 BIT(7)
#define ISP3X_3A_RAWAF_SUM BIT(8)
#define ISP3X_3A_RAWAF_LUM BIT(9)
#define ISP35_AWBSYNC_DONE BIT(9)
#define ISP3X_3A_RAWAF BIT(10)
#define ISP3X_3A_RAWAWB BIT(11)
#define ISP3X_3A_DDR_DONE BIT(12)
#define ISP35_W3A_ERR BIT(13)
#define ISP35_AIAWB_DONE BIT(14)
#define ISP3X_ISP_OUT_LINE(a) ((a) & 0x3fff)
#define ISP3X_ISP_OUT_FRM_CNT(a) (((a) >> 14) & 0x3)
#define ISP33_ISP2ENC_FRM_CNT(a) ((a) & 0xff)
@@ -2832,12 +2950,31 @@
#define ISP39_LDCV_OUTPUT_YUV422 BIT(3)
#define ISP39_LDCV_OUTPUT_YUV420 GENMASK(3, 2)
#define ISP39_LDCV_UV_SWAP BIT(4)
#define ISP39_LDCV_LUT_MODE(x) ((x & 0x3) << 24)
#define ISP39_LDCV_LUT_MODE(x) (((x) & 0x3) << 24)
#define ISP39_LDCV_FORCE_UPD BIT(26)
#define ISP39_LDCV_MAP_ERROR BIT(28)
#define ISP39_LDCV_WORKING BIT(30)
#define ISP39_LDCV_EN_SHD BIT(31)
/* AI */
#define ISP35_AIISP_EN BIT(0)
#define ISP35_AIISP_ST BIT(1)
#define ISP35_AIISP_RAW12_MSB BIT(2)
#define ISP35_AIISP_HDR_EN BIT(3)
#define ISP35_AIISP_GIAN_MODE(x) (((x) & 0x3) << 4)
#define ISP35_NPU_CURVE_EN BIT(6)
#define ISP35_AIPRE_IIR_EN BIT(8)
#define ISP35_AIPRE_IIR2DDR_EN BIT(9)
#define ISP35_AIPRE_GAIN_EN BIT(10)
#define ISP35_AIPRE_GIAN2DDR_EN BIT(11)
#define ISP35_AIPRE_YRAW_SEL BIT(12)
#define ISP35_AIPRE_NL_DDR_MODE BIT(13)
#define ISP35_AIPRE_GAIN_BYPASS BIT(14)
#define ISP35_AIPRE_GAIN_MODE BIT(15)
#define ISP35_AIPRE_NARMAP_INV BIT(16)
#define ISP35_AIPRE_LUMA2GAIN_DIS BIT(17)
#define ISP35_AIPRE_ITS_FORCE_UPD BIT(24)
/* mi interrupt */
#define ISP3X_MI_MP_FRAME BIT(0)
#define ISP3X_MI_SP_FRAME BIT(1)
@@ -2913,6 +3050,8 @@
#define ISP32_MI_OUTPUT_YUV400 0
#define ISP32_MI_OUTPUT_YUV420 BIT(8)
#define ISP32_MI_OUTPUT_YUV422 BIT(9)
#define ISP35_MI_MP_TILE BIT(12)
#define ISP35_MI_SP_TILE BIT(13)
/* MI_WR_CTRL2_SHD */
#define ISP32_BP_EN_IN_SHD BIT(4)
@@ -3019,6 +3158,8 @@
/* CSI2RX */
#define ISP3X_RXSELF_FORCE_UPD BIT(31)
#define ISP35_RXS_FORCE_UPD BIT(31)
#define ISP35_RX0_FORCE_UPD BIT(30)
/* DEBAYER */
@@ -3041,6 +3182,7 @@
/* BLS */
#define ISP32_BLS_BLS2_EN BIT(5)
#define ISP35_BLS_BLS3_EN BIT(6)
/* BAY3D */
#define ISP32_BAY3D_BWSAVING(a) (((a) & 0x1) << 13)
@@ -3053,6 +3195,14 @@
#define ISP3X_LDCH_MAP_ERR BIT(29)
#define ISP3X_LDCH_FORCE_UPD BIT(31)
#define ISP35_B3DLDC_EN BIT(0)
#define ISP35_B3DLDC_MAP_ERR BIT(12)
#define ISP35_B3DLDC_LUT_MODE(x) (((x) & 0x3) << 24)
#define ISP35_B3DLDC_FORCE_UPD BIT(26)
#define ISP35_B3DLDHC_LUT_FRM_END BIT(8)
#define ISP35_B3DLDCH_MAP_ERR BIT(29)
/* DHAZ */
#define ISP3X_DHAZ_ENMUX BIT(0)
#define ISP3X_DHAZ_DC_EN BIT(4)
@@ -3115,6 +3265,12 @@
#define ISP3X_3DLUT_LUT_MODE(x) (((x) & 0x3) << 24)
#define ISP3X_3DLUT_LUT_ERR BIT(29)
#define ISP35_HSV_FIX_RW_CONFLICT BIT(8)
#define ISP35_HSV_AHB_CFG_LUT_EN BIT(9)
/* AWBSYNC */
#define ISP35_AWBSYNC_FRM_PROT BIT(1)
/* DEBAYER */
/* LSC */
@@ -3133,6 +3289,9 @@
#define ISP39_W3A_PDAF2DDR_HOLD_DIS BIT(3)
#define ISP39_W3A_AUTO_CLR_EN BIT(4)
#define ISP39_W3A_CLK_GATING_DIS BIT(5)
#define ISP35_W3A_B3DNROUT_ILG_BYPASS BIT(8)
#define ISP35_W3A_RAWLSC_SEL BIT(9)
#define ISP35_W3A_FORCE_UPD_F BIT(30)
#define ISP39_W3A_FORCE_UPD BIT(31)
#define ISP39_W3A_INT_AEBIG BIT(0)
@@ -3198,4 +3357,12 @@
#define ISP32_RAWAWB_2DDR_PATH_DS BIT(27)
#define ISP32_RAWAWB_2DDR_PATH_ERR BIT(29)
#define ISP33_RAWAWB_WRAM_CLR BIT(31)
/* AIAWB */
#define ISP35_AIAWB_EN BIT(0)
#define ISP35_AIAWB_FRMEND_UPD_DIS BIT(28)
#define ISP35_AIAWB_SYS_UPD_DIS BIT(29)
#define ISP35_AIAWB_SELF_UPD BIT(30)
#endif /* _RKISP_REGS_V3X_H */

117
drivers/media/platform/rockchip/isp/rkisp.c
View File

@@ -239,13 +239,18 @@ int rkisp_align_sensor_resolution(struct rkisp_device *dev,
max_h = dev->hw_dev->unite ?
CIF_ISP_INPUT_H_MAX_V33_UNITE : CIF_ISP_INPUT_H_MAX_V33;
break;
case ISP_V35:
max_w = CIF_ISP_INPUT_W_MAX_V35;
max_h = CIF_ISP_INPUT_H_MAX_V35;
break;
default:
max_w = CIF_ISP_INPUT_W_MAX;
max_h = CIF_ISP_INPUT_H_MAX;
}
max_size = max_w * max_h;
w = clamp_t(u32, src_w, CIF_ISP_INPUT_W_MIN, max_w);
max_h = max_size / w;
if (dev->isp_ver != ISP_V35)
max_h = max_size / w;
h = clamp_t(u32, src_h, CIF_ISP_INPUT_H_MIN, max_h);
if (dev->isp_ver >= ISP_V33) {
@@ -628,12 +633,7 @@ static void rkisp_update_list_reg(struct rkisp_device *dev)
/* sensor mode & index */
if (dev->isp_ver >= ISP_V21) {
val = rkisp_read_reg_cache(dev, ISP_ACQ_H_OFFS);
if (hw->unite == ISP_UNITE_ONE &&
dev->isp_ver == ISP_V33 && !dev->is_frm_rd &&
dev->unite_index == ISP_UNITE_RIGHT)
index = 1;
else
index = dev->multi_index;
index = dev->multi_index;
val |= ISP21_SENSOR_INDEX(index);
if (dev->isp_ver >= ISP_V32_L)
val |= ISP32L_SENSOR_MODE(dev->multi_mode);
@@ -658,7 +658,7 @@ static void rkisp_update_list_reg(struct rkisp_device *dev)
rkisp_update_regs(dev, ISP3X_CAC_PSF_PARA, ISP32_CAC_RO_CNT);
rkisp_update_regs(dev, ISP_LSC_XGRAD_01, ISP3X_CAC_CTRL);
rkisp_update_regs(dev, ISP39_W3A_CTRL1, ISP3X_RAWAWB_RAM_DATA_BASE);
rkisp_update_regs(dev, ISP32_CAC_RO_CNT, ISP39_W3A_CTRL0);
rkisp_update_regs(dev, ISP32_CAC_RO_CNT, ISP39_W3A_CTRL0 - 4);
if (dev->isp_ver == ISP_V21) {
val = rkisp_read(dev, MI_WR_CTRL2, false);
rkisp_set_bits(dev, MI_WR_CTRL2, 0, val, true);
@@ -666,11 +666,28 @@ static void rkisp_update_list_reg(struct rkisp_device *dev)
} else {
if (dev->isp_ver >= ISP_V32_L)
rkisp_write(dev, ISP32_SELF_SCALE_UPDATE, ISP32_SCALE_FORCE_UPD, true);
if (dev->isp_ver == ISP_V33 || dev->isp_ver == ISP_V39) {
if (dev->isp_ver >= ISP_V33) {
rkisp_write(dev, ISP39_MAIN_SCALE_UPDATE, ISP32_SCALE_FORCE_UPD, true);
if (dev->isp_ver == ISP_V33)
rkisp_write(dev, ISP33_BP_SCALE_UPDATE, ISP32_SCALE_FORCE_UPD, true);
}
if (dev->isp_ver == ISP_V35) {
rkisp_update_regs(dev, ISP35_AIAWB_CTRL1, ISP35_AIAWB_WR_BASE_VIR);
val = rkisp_read(dev, ISP35_AIAWB_CTRL0, false);
if (val & ISP35_AIAWB_EN) {
val |= ISP35_AIAWB_SELF_UPD;
writel(val, hw->base_addr + ISP35_AIAWB_CTRL0);
}
if (rkisp_read(dev, ISP39_W3A_CTRL0, false) & ISP39_W3A_EN) {
val = rkisp_read(dev, ISP3X_SWS_CFG, false);
val |= ISP3X_3A_DDR_WRITE_EN;
writel(val, hw->base_addr + ISP3X_SWS_CFG);
}
}
if (dev->isp_ver >= ISP_V33) {
val = rkisp_read(dev, ISP39_W3A_CTRL0, false);
writel(val, hw->base_addr + ISP39_W3A_CTRL0);
}
rkisp_unite_write(dev, ISP3X_MI_WR_INIT, CIF_MI_INIT_SOFT_UPD, true);
}
v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev,
@@ -914,7 +931,7 @@ run_next:
/* disable isp force update to read 3dlut
* 3dlut auto update at frame end for single sensor
*/
if (hw->is_single && is_upd &&
if (hw->is_single && is_upd && hw->isp_ver < ISP_V33 &&
rkisp_read_reg_cache(dev, ISP_3DLUT_UPDATE) & 0x1) {
rkisp_unite_write(dev, ISP_3DLUT_UPDATE, 0, true);
is_3dlut_upd = true;
@@ -960,6 +977,13 @@ run_next:
udelay(25);
}
if (hw->isp_ver == ISP_V35) {
val = rkisp_read_reg_cache(dev, ISP3X_CSI2RX_RAW_RD_CTRL);
val |= ISP35_RXS_FORCE_UPD;
if (dev->rd_mode == HDR_RDBK_FRAME2)
val |= ISP35_RX0_FORCE_UPD;
writel(val, hw->base_addr + ISP3X_CSI2RX_RAW_RD_CTRL);
}
val = rkisp_read(dev, CSI2RX_CTRL0, true);
val &= ~SW_IBUF_OP_MODE(0xf);
tmp = SW_IBUF_OP_MODE(dev->rd_mode);
@@ -1445,7 +1469,7 @@ static void rkisp_config_ism(struct rkisp_device *dev)
rkisp_unite_write(dev, CIF_ISP_IS_V_SIZE, height / mult, false);
if (dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32 ||
dev->isp_ver == ISP_V33)
dev->isp_ver >= ISP_V33)
return;
/* IS(Image Stabilization) is always on, working as output crop */
@@ -1457,8 +1481,7 @@ static int rkisp_reset_handle(struct rkisp_device *dev)
u32 val;
dev_info(dev->dev, "%s enter\n", __func__);
if (dev->isp_ver == ISP_V39 && dev->sditf_dev && dev->sditf_dev->is_on)
rkisp_sditf_reset_notify_vpss(dev);
rkisp_sditf_reset_notify_vpss(dev);
rkisp_hw_reg_save(dev->hw_dev);
rkisp_soft_reset(dev->hw_dev, true);
@@ -2919,6 +2942,9 @@ static void rkisp_isp_sd_try_crop(struct v4l2_subdev *sd,
case ISP_V33:
size = CIF_ISP_INPUT_W_MAX_V33 * CIF_ISP_INPUT_H_MAX_V33;
break;
case ISP_V35:
size = CIF_ISP_INPUT_W_MAX_V35 * CIF_ISP_INPUT_H_MAX_V35;
break;
case ISP_V39:
size = CIF_ISP_INPUT_W_MAX_V39_UNITE * CIF_ISP_INPUT_H_MAX_V39_UNITE;
size /= 2;
@@ -3006,6 +3032,10 @@ static int rkisp_isp_sd_get_selection(struct v4l2_subdev *sd,
max_h = dev->hw_dev->unite ?
CIF_ISP_INPUT_H_MAX_V33_UNITE : CIF_ISP_INPUT_H_MAX_V33;
break;
case ISP_V35:
max_w = CIF_ISP_INPUT_W_MAX_V35;
max_h = CIF_ISP_INPUT_H_MAX_V35;
break;
case ISP_V39:
max_w = dev->hw_dev->unite ?
CIF_ISP_INPUT_W_MAX_V39_UNITE : CIF_ISP_INPUT_W_MAX_V39;
@@ -3765,7 +3795,8 @@ static int rkisp_set_work_mode_by_vicap(struct rkisp_device *isp_dev,
isp_dev->is_suspend_one_frame = false;
if (vicap_mode->rdbk_mode < RKISP_VICAP_RDBK_AIQ) {
if (!hw->is_single && hw->isp_ver != ISP_V33)
if (!hw->is_single &&
hw->isp_ver != ISP_V33 && hw->isp_ver != ISP_V35)
return -EINVAL;
/* switch to online mode for single sensor */
switch (rd_mode) {
@@ -3802,13 +3833,15 @@ static int rkisp_set_work_mode_by_vicap(struct rkisp_device *isp_dev,
rkisp_unite_write(isp_dev, CSI2RX_CTRL0,
SW_IBUF_OP_MODE(isp_dev->rd_mode), true);
mask = SW_MPIP_DROP_FRM_DIS;
if (isp_dev->isp_ver == ISP_V33)
if (isp_dev->isp_ver == ISP_V33 || isp_dev->isp_ver == ISP_V35)
mask |= ISP33_SW_ISP2ENC_PATH_EN | ISP33_PP_ENC_PIPE_EN;
if (IS_HDR_RDBK(isp_dev->rd_mode)) {
val = SW_MPIP_DROP_FRM_DIS;
if (isp_dev->isp_ver == ISP_V33 && isp_dev->cap_dev.wrap_line)
if (isp_dev->cap_dev.wrap_line &&
(isp_dev->isp_ver == ISP_V33 || isp_dev->isp_ver == ISP_V35))
val = ISP33_SW_ISP2ENC_PATH_EN | ISP33_PP_ENC_PIPE_EN;
} else if (isp_dev->isp_ver == ISP_V33 && isp_dev->cap_dev.wrap_line) {
} else if (isp_dev->cap_dev.wrap_line &&
(isp_dev->isp_ver == ISP_V33 || isp_dev->isp_ver == ISP_V35)) {
val = ISP33_SW_ISP2ENC_PATH_EN;
} else {
val = 0;
@@ -4027,7 +4060,8 @@ static int rkisp_set_online_hdr_wrap(struct rkisp_device *dev, int *line)
"hdr wrap no support for offline\n");
return -EINVAL;
}
if (dev->isp_ver != ISP_V33 || dev->unite_div != ISP_UNITE_DIV1) {
if (dev->unite_div != ISP_UNITE_DIV1 ||
(dev->isp_ver != ISP_V33 && dev->isp_ver != ISP_V35)) {
v4l2_warn(&dev->v4l2_dev,
"hdr wrap support for 1103b and no unite mode\n");
return -EINVAL;
@@ -4142,8 +4176,6 @@ static long rkisp_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
{
struct rkisp_device *isp_dev = sd_to_isp_dev(sd);
struct rkisp_thunderboot_resmem *resmem;
struct rkisp32_thunderboot_resmem_head *tb_head_v32;
struct rkisp33_thunderboot_resmem_head *tb_head_v33;
struct rkisp_thunderboot_resmem_head *head;
struct rkisp_thunderboot_shmem *shmem;
struct isp2x_buf_idxfd *idxfd;
@@ -4164,31 +4196,29 @@ static long rkisp_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
rkisp_get_info(isp_dev, arg);
break;
case RKISP_CMD_GET_TB_HEAD_V32:
if (isp_dev->tb_head.complete != RKISP_TB_OK ||
(!isp_dev->is_rtt_suspend && !isp_dev->is_pre_on)) {
ret = -EINVAL;
break;
}
tb_head_v32 = arg;
memcpy(tb_head_v32, &isp_dev->tb_head,
sizeof(struct rkisp_thunderboot_resmem_head));
memcpy(&tb_head_v32->cfg, isp_dev->params_vdev.isp32_params,
sizeof(struct isp32_isp_params_cfg));
break;
case RKISP_CMD_GET_TB_HEAD_V33:
case RKISP_CMD_GET_TB_HEAD:
if (isp_dev->tb_head.complete != RKISP_TB_OK ||
(!isp_dev->is_rtt_suspend && !isp_dev->is_pre_on)) {
ret = -EINVAL;
break;
}
tb_head_v33 = arg;
memcpy(tb_head_v33, &isp_dev->tb_head,
memcpy(arg, &isp_dev->tb_head,
sizeof(struct rkisp_thunderboot_resmem_head));
memcpy(&tb_head_v33->cfg, isp_dev->params_vdev.isp33_params,
sizeof(struct isp33_isp_params_cfg));
if (cmd != RKISP_CMD_GET_TB_HEAD_V32 && cmd != RKISP_CMD_GET_TB_HEAD_V33)
break;
if (cmd == RKISP_CMD_GET_TB_HEAD_V32)
memcpy(arg + sizeof(struct rkisp_thunderboot_resmem_head),
isp_dev->params_vdev.isp32_params,
sizeof(struct isp32_isp_params_cfg));
else
memcpy(arg + sizeof(struct rkisp_thunderboot_resmem_head),
isp_dev->params_vdev.isp33_params,
sizeof(struct isp33_isp_params_cfg));
break;
case RKISP_CMD_SET_TB_HEAD_V32:
case RKISP_CMD_SET_TB_HEAD_V33:
case RKISP_CMD_SET_TB_HEAD:
memcpy(&isp_dev->tb_head, arg,
sizeof(struct rkisp_thunderboot_resmem_head));
break;
@@ -4325,6 +4355,9 @@ static long rkisp_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
case RKISP_VICAP_CMD_SOF:
ret = rkisp_vicap_sof(isp_dev, arg);
break;
case RKISP_CMD_AIAWB_BUF:
ret = rkisp_params_get_aiawb_buffd(&isp_dev->params_vdev, arg);
break;
default:
ret = -ENOIOCTLCMD;
}
@@ -4435,6 +4468,11 @@ static long rkisp_compat_ioctl32(struct v4l2_subdev *sd,
size = sizeof(struct rkisp_fpn_cfg);
cp_f_us = true;
break;
case RKISP_CMD_AIAWB_BUF:
size = sizeof(struct rkisp_aiawb_buffd);
cp_f_us = true;
cp_t_us = true;
break;
default:
return -ENOIOCTLCMD;
}
@@ -4636,6 +4674,8 @@ void rkisp_save_tb_info(struct rkisp_device *isp_dev)
offset = size * isp_dev->dev_id;
break;
default:
size = sizeof(struct rkisp_thunderboot_resmem_head);
offset = size * isp_dev->dev_id;
break;
}
@@ -4664,6 +4704,8 @@ void rkisp_save_tb_info(struct rkisp_device *isp_dev)
tmp->cfg.module_en_update,
tmp->cfg.module_ens,
tmp->cfg.module_cfg_update);
} else {
head = resmem_va + offset;
}
if (param && (isp_dev->isp_state & ISP_STOP)) {
params_vdev->ops->get_param_size(params_vdev,
@@ -4691,8 +4733,7 @@ void rkisp_chk_tb_over(struct rkisp_device *isp_dev)
if (!isp_dev->is_thunderboot)
return;
if (params_vdev->is_first_cfg &&
(isp_dev->isp_ver == ISP_V32 || isp_dev->isp_ver == ISP_V33))
if (params_vdev->is_first_cfg)
goto end;
resmem_va = phys_to_virt(isp_dev->resmem_pa);
@@ -4930,7 +4971,7 @@ void rkisp_isp_isr(unsigned int isp_mis,
/* disabled frame end to read 3dlut for multi sensor
* 3dlut will update at isp readback
*/
if (!dev->hw_dev->is_single) {
if (!dev->hw_dev->is_single && dev->isp_ver < ISP_V33) {
writel(0, hw->base_addr + ISP_3DLUT_UPDATE);
if (hw->unite == ISP_UNITE_TWO)
writel(0, hw->base_next_addr + ISP_3DLUT_UPDATE);

2
drivers/media/platform/rockchip/isp/rkisp.h
View File

@@ -71,6 +71,8 @@
#define CIF_ISP_INPUT_H_MAX_V33 1620
#define CIF_ISP_INPUT_W_MAX_V33_UNITE 3840
#define CIF_ISP_INPUT_H_MAX_V33_UNITE 2160
#define CIF_ISP_INPUT_W_MAX_V35 4096
#define CIF_ISP_INPUT_H_MAX_V35 3072
#define CIF_ISP_INPUT_W_MIN 272
#define CIF_ISP_INPUT_H_MIN 264
#define CIF_ISP_OUTPUT_W_MAX CIF_ISP_INPUT_W_MAX

4
include/soc/rockchip/rockchip_rockit.h
View File

@@ -125,7 +125,9 @@ struct rockit_rkcif_cfg {
int (*rkcif_rockit_mpibuf_done)(struct rockit_rkcif_cfg *rockit_cif_cfg);
};
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V32) || IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V33)
#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V32) || \
IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V33) || \
IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V35)
void *rkisp_rockit_function_register(void *function, int cmd);
int rkisp_rockit_get_ispdev(char **name);

26
include/uapi/linux/rk-isp2-config.h
View File

@@ -91,6 +91,15 @@
#define RKISP_CMD_INIT_BNR_BUF \
_IOWR('V', BASE_VIDIOC_PRIVATE + 26, struct rkisp_bnr_buf_info)
#define RKISP_CMD_GET_TB_HEAD \
_IOR('V', BASE_VIDIOC_PRIVATE + 27, struct rkisp_thunderboot_resmem_head)
#define RKISP_CMD_SET_TB_HEAD \
_IOW('V', BASE_VIDIOC_PRIVATE + 28, struct rkisp_thunderboot_resmem_head)
#define RKISP_CMD_AIAWB_BUF \
_IOWR('V', BASE_VIDIOC_PRIVATE + 29, struct rkisp_aiawb_buffd)
/****************ISP VIDEO IOCTL******************************/
#define RKISP_CMD_GET_CSI_MEMORY_MODE \
@@ -141,6 +150,7 @@
/* BASE_VIDIOC_PRIVATE + 115 for RKISP_CMD_GET_PARAMS_V39 */
/* BASE_VIDIOC_PRIVATE + 116 for RKISP_CMD_GET_PARAMS_V33 */
/* BASE_VIDIOC_PRIVATE + 117 for RKISP_CMD_SET_QUICK_STREAM */
/* BASE_VIDIOC_PRIVATE + 119 for RKISP_CMD_GET_PARAMS_V35 */
/* frame information attach to image tail, see struct rkisp_frame_info
* set this before VIDIOC_REQBUFS then VIDIOC_QUERYBUF to get buf size
@@ -330,6 +340,21 @@ struct rkisp_buf_info {
int buf_fd[RKISP_BUFFER_MAX];
} __attribute__ ((packed));
enum rkisp_aiawb_ds {
RKISP_AIAWB_DS_4X4,
RKISP_AIAWB_DS_8X4,
RKISP_AIAWB_DS_8X8,
RKISP_AIAWB_DS_16X16,
};
/* struct rkisp_aiawb_buffd
* set aiawb buf count and get buf fd result
*/
struct rkisp_aiawb_buffd {
enum rkisp_aiawb_ds ds;
struct rkisp_buf_info info;
} __attribute__ ((packed));
enum rkisp_isp_mode {
/* frame input related */
RKISP_ISP_NORMAL = _BITUL(0),
@@ -372,6 +397,7 @@ struct rkisp_meshbuf_size {
struct isp2x_mesh_head {
enum isp2x_mesh_buf_stat stat;
__u32 data_oft;
__u32 data1_oft;
} __attribute__ ((packed));
enum {

1751
include/uapi/linux/rk-isp35-config.h Normal file
View File

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