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Merge commit 'beb9974b6fb001eb197b613257ef57fd603db652'

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* commit 'beb9974b6fb001eb197b613257ef57fd603db652':
  media: i2c: sc850sl: fix gain discontinuity issue
  media: rockchip: isp: fix resume mi no enable

Change-Id: If8e1a2004de712a6b59d64206f2a26bb92b92ea7
This commit is contained in:
Tao Huang
2024-01-15 15:02:59 +08:00
parent 5a80764225 beb9974b6f
commit d847fc30ee
3 changed files with 59 additions and 14 deletions
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31
drivers/media/i2c/sc850sl.c
View File

@@ -73,7 +73,7 @@
#define SC850SL_REG_DGAIN 0x3e06
#define SC850SL_REG_AGAIN 0x3e08
#define SC850SL_REG_AGAIN_FINE 0x3e09
//#define SC850SL_REG_DGAIN_FINE 0x3e07
#define SC850SL_REG_DGAIN_FINE 0x3e07
//short fram gain reg
#define SC850SL_SF_REG_AGAIN 0x3e12
@@ -370,7 +370,6 @@ static __maybe_unused const struct regval sc850sl_linear10bit_3840x2160_regs[] =
{0x59fd, 0x3f},
{0x59fe, 0x38},
{0x59ff, 0x30},
{0x0100, 0x01},
/*
* [gain < 2x] {0x363c, 0x05},
* [gain >=2x] {0x363c, 0x07},
@@ -700,7 +699,7 @@ static void sc850sl_get_module_inf(struct sc850sl *sc850sl,
}
static void sc850sl_get_gain_reg(u32 val, u32 *again_reg, u32 *again_fine_reg,
u32 *dgain_reg)
u32 *dgain_reg, u32 *dgain_fine_reg)
{
u8 u8Reg0x3e09 = 0x40, u8Reg0x3e08 = 0x03;
u32 aCoarseGain = 0;
@@ -744,16 +743,19 @@ static void sc850sl_get_gain_reg(u32 val, u32 *again_reg, u32 *again_fine_reg,
u8Reg0x3e09 = aFineGain;
//dcg = 2.72  -->  2.72*1024=2785.28
u8Reg0x3e08 = (again > 200) ? (u8Reg0x3e08 | 0x20) : (u8Reg0x3e08 & 0x1f);
*dgain_fine_reg = val * 128 / again / dgain;
//dgain
if (dgain <= 1) { /*1x ~ 2x*/
if (dgain < 2) { /*1x ~ 2x*/
*dgain_reg = 0x00;
} else if (dgain <= 2) { /*2x ~ 4x*/
} else if (dgain < 4) { /*2x ~ 4x*/
*dgain_reg = 0x01;
} else if (dgain <= 4) { /*4x ~ 8x*/
*dgain_fine_reg += (dgain - 2) * 64;
} else if (dgain < 8) { /*4x ~ 8x*/
*dgain_reg = 0x03;
*dgain_fine_reg += (dgain - 4) * 32;
} else {
*dgain_reg = 0x07;
*dgain_fine_reg = 0x80;
}
*again_reg = u8Reg0x3e08;
@@ -1334,7 +1336,7 @@ static int sc850sl_set_ctrl(struct v4l2_ctrl *ctrl)
struct sc850sl, ctrl_handler);
struct i2c_client *client = sc850sl->client;
s64 max;
u32 again, again_fine, dgain;
u32 again, again_fine, dgain, dgain_fine;
int ret = 0;
u32 val;
@@ -1342,7 +1344,7 @@ static int sc850sl_set_ctrl(struct v4l2_ctrl *ctrl)
switch (ctrl->id) {
case V4L2_CID_VBLANK:
/* Update max exposure while meeting expected vblanking */
max = sc850sl->cur_mode->height + ctrl->val - 8;
max = sc850sl->cur_mode->height + ctrl->val - 4;
__v4l2_ctrl_modify_range(sc850sl->exposure,
sc850sl->exposure->minimum, max,
sc850sl->exposure->step,
@@ -1376,9 +1378,10 @@ static int sc850sl_set_ctrl(struct v4l2_ctrl *ctrl)
case V4L2_CID_ANALOGUE_GAIN:
if (sc850sl->cur_mode->hdr_mode != NO_HDR)
goto out_ctrl;
sc850sl_get_gain_reg(ctrl->val, &again, &again_fine, &dgain);
dev_dbg(&client->dev, "recv_gain:%d set again 0x%x, again_fine 0x%x, set dgain 0x%x\n",
ctrl->val, again, again_fine, dgain);
sc850sl_get_gain_reg(ctrl->val, &again, &again_fine, &dgain, &dgain_fine);
dev_dbg(&client->dev,
"recv_gain:%d set again 0x%x, again_fine 0x%x, set dgain 0x%x, dgain_fine 0x%x\n",
ctrl->val, again, again_fine, dgain, dgain_fine);
ret |= sc850sl_write_reg(sc850sl->client,
SC850SL_REG_AGAIN,
@@ -1392,6 +1395,10 @@ static int sc850sl_set_ctrl(struct v4l2_ctrl *ctrl)
SC850SL_REG_DGAIN,
SC850SL_REG_VALUE_08BIT,
dgain);
ret |= sc850sl_write_reg(sc850sl->client,
SC850SL_REG_DGAIN_FINE,
SC850SL_REG_VALUE_08BIT,
dgain_fine);
break;
case V4L2_CID_VBLANK:
ret = sc850sl_write_reg(sc850sl->client, SC850SL_REG_VTS,

40
drivers/media/platform/rockchip/isp/hw.c
View File

@@ -395,6 +395,9 @@ void rkisp_hw_reg_restore(struct rkisp_hw_dev *dev)
}, {
.base = MI_GAIN_WR_BASE,
.shd = MI_GAIN_WR_BASE_SHD,
}, {
.base = MI_WR_CTRL,
.shd = MI_WR_CTRL_SHD,
}
};
@@ -449,7 +452,34 @@ void rkisp_hw_reg_restore(struct rkisp_hw_dev *dev)
reg = reg_buf + backup[j].base;
reg1 = reg_buf + backup[j].shd;
backup[j].val = *reg;
writel(*reg1, base + backup[j].base);
if (backup[j].base == MI_WR_CTRL) {
val = *reg1 & 0xf;
val |= (*reg & ~0xf);
} else {
val = *reg1;
}
writel(val, base + backup[j].base);
}
if (dev->isp_ver == ISP_V30) {
reg = reg_buf + ISP32_MI_WR_CTRL2_SHD;
reg1 = reg_buf + ISP3X_MI_BP_WR_CTRL;
if ((*reg & ISP32_BP_EN_IN_SHD) != (*reg1 & ISP3X_BP_ENABLE)) {
val = *reg & ISP32_BP_EN_IN_SHD;
val |= *reg1 & ~ISP3X_BP_ENABLE;
writel(val, base + ISP3X_MI_BP_WR_CTRL);
}
reg1 = reg_buf + ISP32_MI_MPDS_WR_CTRL;
if ((*reg & ISP32_MPDS_EN_IN_SHD) != (*reg1 & ISP32_DS_ENABLE)) {
val = *reg & ISP32_MPDS_EN_IN_SHD;
val |= *reg1 & ~ISP32_DS_ENABLE;
writel(val, base + ISP32_MI_MPDS_WR_CTRL);
}
reg1 = reg_buf + ISP32_MI_BPDS_WR_CTRL;
if ((*reg & ISP32_BPDS_EN_IN_SHD) != (*reg1 & ISP32_DS_ENABLE)) {
val = *reg & ISP32_BPDS_EN_IN_SHD;
val |= *reg1 & ~ISP32_DS_ENABLE;
writel(val, base + ISP32_MI_BPDS_WR_CTRL);
}
}
/* update module */
@@ -476,6 +506,14 @@ void rkisp_hw_reg_restore(struct rkisp_hw_dev *dev)
/* config base_reg */
for (j = 0; j < ARRAY_SIZE(backup); j++)
writel(backup[j].val, base + backup[j].base);
if (dev->isp_ver == ISP_V30) {
reg = reg_buf + ISP3X_MI_BP_WR_CTRL;
writel(*reg, base + ISP3X_MI_BP_WR_CTRL);
reg = reg_buf + ISP32_MI_MPDS_WR_CTRL;
writel(*reg, base + ISP32_MI_MPDS_WR_CTRL);
reg = reg_buf + ISP32_MI_BPDS_WR_CTRL;
writel(*reg, base + ISP32_MI_BPDS_WR_CTRL);
}
/* base_reg = shd_reg, write is base but read is shd */
val = rkisp_read_reg_cache(isp, ISP_MPFBC_HEAD_PTR);
writel(val, base + ISP_MPFBC_HEAD_PTR);

2
drivers/media/platform/rockchip/isp/isp_rockit.c
View File

@@ -192,7 +192,7 @@ int rkisp_rockit_buf_queue(struct rockit_cfg *input_rockit_cfg)
isprk_buf->isp_buf.buff_addr[0], isprk_buf->isp_buf.buff_addr[1]);
/* single sensor with pingpong buf, update next if need */
if (stream->ispdev->hw_dev->is_single &&
if (ispdev->hw_dev->is_single && !ispdev->is_suspend &&
stream->id != RKISP_STREAM_VIR &&
stream->id != RKISP_STREAM_LUMA &&
stream->streaming && !stream->next_buf) {