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rk3288: fix the bug when dclk_lcdc select gpll as parent

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dkl
2014-04-30 18:14:35 +08:00
parent db27b82256
commit d86c0abe7f
1 changed files with 2 additions and 0 deletions
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2
drivers/clk/rockchip/clk-ops.c
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@@ -572,6 +572,7 @@ static long clk_3288_dclk_lcdc0_determine_rate(struct clk_hw *hw, unsigned long
if((rate <= (297*MHZ)) && ((297*MHZ)%rate == 0)) {
*best_parent_p = gpll;
best = rate;
*best_parent_rate = 297*MHZ;
} else {
*best_parent_p = cpll;
div = RK3288_LIMIT_PLL_VIO0/rate;
@@ -630,6 +631,7 @@ static long clk_3288_dclk_lcdc1_determine_rate(struct clk_hw *hw, unsigned long
if((rate <= (297*MHZ)) && ((297*MHZ)%rate == 0)) {
*best_parent_p = gpll;
best = rate;
*best_parent_rate = 297*MHZ;
} else {
*best_parent_p = cpll;
div = RK3288_LIMIT_PLL_VIO1/rate;