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arm64: dts: rockchip: rk3399: add dclk pll sources

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Change-Id: I0e29d67d5e3738b18a7407a049d216f8dcebb8e8
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
This commit is contained in:
Mark Yao
2017-06-12 15:24:32 +08:00
committed by Jianqun Xu
parent 92ac4e68b2
commit d8a4f839b9
1 changed files with 6 additions and 4 deletions
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10
arch/arm64/boot/dts/rockchip/rk3399.dtsi
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@@ -162,6 +162,8 @@
display-subsystem {
compatible = "rockchip,display-subsystem";
ports = <&vopl_out>, <&vopb_out>;
clocks = <&cru PLL_VPLL>, <&cru PLL_CPLL>;
clock-names = "hdmi-tmds-pll", "default-vop-pll";
};
pmu_a53 {
@@ -1697,8 +1699,8 @@
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
assigned-clock-rates = <400000000>, <100000000>;
clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>, <&cru DCLK_VOP1_DIV>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop", "dclk_source";
iommus = <&vopl_mmu>;
power-domains = <&power RK3399_PD_VOPL>;
resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
@@ -1768,8 +1770,8 @@
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
assigned-clock-rates = <400000000>, <100000000>;
clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>, <&cru DCLK_VOP0_DIV>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop", "dclk_source";
iommus = <&vopb_mmu>;
power-domains = <&power RK3399_PD_VOPB>;
resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;