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video: rockchip: rga3: fix ovlap non-16 alignment lost alpha channel

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When in ABB mode, ovlap needs to enable top/bottom alpha read enable
at the same time.
Because ovlap_offset is not 16 aligned, the bottom will be read in
16*16 blocks. If alpha reading is not enabled at this time, this part
 of the alpha channel will be lost.

Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Change-Id: Id18328e4385064d6be7e0574e344cc5413d20df0
This commit is contained in:
Yu Qiaowei
2022-08-30 15:52:28 +08:00
parent a81422efff
commit d8e05d0f1b
1 changed files with 12 additions and 4 deletions
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16
drivers/video/rockchip/rga3/rga3_reg_info.c
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@@ -1305,9 +1305,13 @@ void rga_cmd_to_rga3_cmd(struct rga_req *req_rga, struct rga3_req *req)
* dst => wr
*/
/* enabled by default bot_blend_m1 && bot_alpha_cal_m1 for src channel(win0) */
/*
* enabled by default bot_blend_m1 && bot_alpha_cal_m1 for src channel(win0)
* In ABB mode, the number will be fetched according to 16*16, so it needs to
* be enabled top_blend_m1 && top_alpha_cal_m1 for dst channel(wr).
*/
if (rga_is_alpha_format(req_rga->src.format))
req->alpha_mode_1 = 0x0a00;
req->alpha_mode_1 = 0x0a0a;
set_win_info(&req->win0, &req_rga->src);
@@ -1331,9 +1335,13 @@ void rga_cmd_to_rga3_cmd(struct rga_req *req_rga, struct rga3_req *req)
* dst => wr
*/
/* enabled by default top_blend_m1 && top_alpha_cal_m1 for src channel(win1) */
/*
* enabled by default top_blend_m1 && top_alpha_cal_m1 for src channel(win1)
* In ABB mode, the number will be fetched according to 16*16, so it needs to
* be enabled bot_blend_m1 && bot_alpha_cal_m1 for src1/dst channel(win0).
*/
if (rga_is_alpha_format(req_rga->src.format))
req->alpha_mode_1 = 0x0a;
req->alpha_mode_1 = 0x0a0a;
if (req_rga->pat.yrgb_addr != 0) {
if (req_rga->src.yrgb_addr == req_rga->dst.yrgb_addr) {