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arm64: dts: rockchip: add sata support for RK3568

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Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: Icddec5869b42f301655d1d9fbd55a5d661f3866b
This commit is contained in:
Yifeng Zhao
2020-10-22 17:36:19 +08:00
committed by Tao Huang
parent a7d08921b1
commit d95f0b78c9
1 changed files with 45 additions and 0 deletions
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45
arch/arm64/boot/dts/rockchip/rk3568.dtsi
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@@ -121,6 +121,51 @@
clock-output-names = "xin24m";
};
sata0: sata@fc000000 {
compatible = "snps,dwc-ahci";
reg = <0 0xfc300000 0 0x1000>;
clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>,
<&cru CLK_SATA0_RXOOB>;
clock-names = "sata", "pmalive", "rxoob";
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hostc";
phys = <&combphy0_us PHY_TYPE_SATA>;
phy-names = "sata-phy";
ports-implemented = <0x1>;
power-domains = <&power RK3568_PD_PIPE>;
status = "disabled";
};
sata1: sata@fc400000 {
compatible = "snps,dwc-ahci";
reg = <0 0xfc340000 0 0x1000>;
clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>,
<&cru CLK_SATA1_RXOOB>;
clock-names = "sata", "pmalive", "rxoob";
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hostc";
phys = <&combphy1_usq PHY_TYPE_SATA>;
phy-names = "sata-phy";
ports-implemented = <0x1>;
power-domains = <&power RK3568_PD_PIPE>;
status = "disabled";
};
sata2: sata@fc800000 {
compatible = "snps,dwc-ahci";
reg = <0 0xfc380000 0 0x1000>;
clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>,
<&cru CLK_SATA2_RXOOB>;
clock-names = "sata", "pmalive", "rxoob";
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hostc";
phys = <&combphy2_psq PHY_TYPE_SATA>;
phy-names = "sata-phy";
ports-implemented = <0x1>;
power-domains = <&power RK3568_PD_PIPE>;
status = "disabled";
};
usbdrd30: usbdrd {
compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3";
clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>,