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scsi: ufs: rockchip: add support for rk3576
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Change-Id: I12085a4a50d28eb4d389327771449ecc190e6eb7
This commit is contained in:
Yifeng Zhao
@@ -125,3 +125,15 @@ config SCSI_UFS_EXYNOS
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Select this if you have UFS host controller on Samsung Exynos SoC.
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If unsure, say N.
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config SCSI_UFS_ROCKCHIP
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tristate "Rockchip specific hooks to UFS controller platform driver"
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depends on SCSI_UFSHCD_PLATFORM && (ARCH_ROCKCHIP || COMPILE_TEST)
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help
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This selects the Rockchip specific additions to UFSHCD platform driver.
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UFS host on Rockchip needs some vendor specific configuration before
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accessing the hardware which includes PHY configuration and vendor
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specific registers.
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Select this if you have UFS controller on Rockchip chipset.
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If unsure, say N.
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@@ -13,3 +13,4 @@ obj-$(CONFIG_SCSI_UFS_HISI) += ufs-hisi.o
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obj-$(CONFIG_SCSI_UFS_MEDIATEK) += ufs-mediatek.o
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obj-$(CONFIG_SCSI_UFS_RENESAS) += ufs-renesas.o
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obj-$(CONFIG_SCSI_UFS_TI_J721E) += ti-j721e-ufs.o
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obj-$(CONFIG_SCSI_UFS_ROCKCHIP) += ufs-rockchip.o
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384
drivers/ufs/host/ufs-rockchip.c
Normal file
384
drivers/ufs/host/ufs-rockchip.c
Normal file
@@ -0,0 +1,384 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Rockchip UFS Host Controller driver
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*
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* Copyright (C) 2024 Rockchip Electronics Co.Ltd.
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*/
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#include <linux/clk.h>
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#include <linux/gpio.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include <ufs/ufshcd.h>
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#include <ufs/unipro.h>
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#include "ufshcd-pltfrm.h"
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#include "ufshcd-dwc.h"
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#include "ufs-rockchip.h"
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static inline bool ufshcd_is_hba_active(struct ufs_hba *hba)
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{
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return ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE;
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}
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static int ufs_rockchip_hce_enable_notify(struct ufs_hba *hba,
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enum ufs_notify_change_status status)
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{
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int err = 0;
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if (status == PRE_CHANGE) {
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int retry_outer = 3;
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int retry_inner;
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start:
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if (ufshcd_is_hba_active(hba))
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/* change controller state to "reset state" */
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ufshcd_hba_stop(hba);
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/* UniPro link is disabled at this point */
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ufshcd_set_link_off(hba);
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/* start controller initialization sequence */
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ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE);
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usleep_range(100, 200);
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/* wait for the host controller to complete initialization */
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retry_inner = 50;
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while (!ufshcd_is_hba_active(hba)) {
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if (retry_inner) {
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retry_inner--;
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} else {
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dev_err(hba->dev,
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"Controller enable failed\n");
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if (retry_outer) {
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retry_outer--;
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goto start;
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}
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return -EIO;
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}
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usleep_range(1000, 1100);
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}
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} else { /* POST_CHANGE */
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err = ufshcd_vops_phy_initialization(hba);
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}
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return err;
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}
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static int ufs_rockchip_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op,
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enum ufs_notify_change_status status)
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{
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struct ufs_rockchip_host *host = ufshcd_get_variant(hba);
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if (status == PRE_CHANGE)
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return 0;
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if (pm_op == UFS_RUNTIME_PM)
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return 0;
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if (host->in_suspend) {
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WARN_ON(1);
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return 0;
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}
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/* set ref clk out disable */
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clk_disable_unprepare(host->ref_out_clk);
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host->in_suspend = true;
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return 0;
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}
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static int ufs_rockchip_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
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{
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struct ufs_rockchip_host *host = ufshcd_get_variant(hba);
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int err;
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if (!host->in_suspend)
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return 0;
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/* set ref clk out enable */
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err = clk_prepare_enable(host->ref_out_clk);
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if (err) {
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dev_err(hba->dev, "failed to enable ref out clock %d\n", err);
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return err;
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}
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host->in_suspend = false;
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return 0;
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}
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static void ufs_rockchip_set_pm_lvl(struct ufs_hba *hba)
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{
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hba->rpm_lvl = UFS_PM_LVL_1;
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hba->spm_lvl = UFS_PM_LVL_3;
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}
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static const unsigned char rk3576_phy_value[15][4] = {
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{0x03, 0x38, 0x50, 0x80},
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{0x03, 0x14, 0x58, 0x80},
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{0x03, 0x26, 0x58, 0x80},
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{0x03, 0x49, 0x58, 0x80},
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{0x03, 0x5A, 0x58, 0x80},
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{0xC3, 0x38, 0x50, 0xC0},
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{0xC3, 0x14, 0x58, 0xC0},
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{0xC3, 0x26, 0x58, 0xC0},
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{0xC3, 0x49, 0x58, 0xC0},
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{0xC3, 0x5A, 0x58, 0xC0},
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{0x43, 0x38, 0x50, 0xC0},
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{0x43, 0x14, 0x58, 0xC0},
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{0x43, 0x26, 0x58, 0xC0},
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{0x43, 0x49, 0x58, 0xC0},
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{0x43, 0x5A, 0x58, 0xC0}
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};
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static int ufs_rockchip_rk3576_phy_init(struct ufs_hba *hba)
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{
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struct ufs_rockchip_host *host = ufshcd_get_variant(hba);
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u32 try_case = host->phy_config_mode, value;
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if (try_case >= ARRAY_SIZE(rk3576_phy_value))
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try_case = 0;
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(PA_LOCAL_TX_LCC_ENABLE, 0x0), 0x0);
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/* enable the mphy DME_SET cfg */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x200, 0x0), 0x40);
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for (int i = 0; i < 2; i++) {
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/* Configuration M-TX */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xaa, SEL_TX_LANE0 + i), 0x06);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xa9, SEL_TX_LANE0 + i), 0x02);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xad, SEL_TX_LANE0 + i), 0x44);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xac, SEL_TX_LANE0 + i), 0xe6);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xab, SEL_TX_LANE0 + i), 0x07);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x94, SEL_TX_LANE0 + i), 0x93);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x93, SEL_TX_LANE0 + i), 0xc9);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x7f, SEL_TX_LANE0 + i), 0x00);
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/* Configuration M-RX */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x12, SEL_RX_LANE0 + i), 0x06);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x11, SEL_RX_LANE0 + i), 0x00);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1d, SEL_RX_LANE0 + i), 0x58);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1c, SEL_RX_LANE0 + i), 0x8c);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1b, SEL_RX_LANE0 + i), 0x02);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x25, SEL_RX_LANE0 + i), 0xf6);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x2f, SEL_RX_LANE0 + i), 0x69);
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}
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/* disable the mphy DME_SET cfg */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x200, 0x0), 0x00);
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ufs_sys_writel(host->mphy_base, 0x80, 0x08C);
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ufs_sys_writel(host->mphy_base, 0xB5, 0x110);
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ufs_sys_writel(host->mphy_base, 0xB5, 0x250);
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value = rk3576_phy_value[try_case][0];
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ufs_sys_writel(host->mphy_base, value, 0x134);
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ufs_sys_writel(host->mphy_base, value, 0x274);
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value = rk3576_phy_value[try_case][1];
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ufs_sys_writel(host->mphy_base, value, 0x0E0);
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ufs_sys_writel(host->mphy_base, value, 0x220);
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value = rk3576_phy_value[try_case][2];
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ufs_sys_writel(host->mphy_base, value, 0x164);
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ufs_sys_writel(host->mphy_base, value, 0x2A4);
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value = rk3576_phy_value[try_case][3];
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ufs_sys_writel(host->mphy_base, value, 0x178);
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ufs_sys_writel(host->mphy_base, value, 0x2B8);
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ufs_sys_writel(host->mphy_base, 0x18, 0x1B0);
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ufs_sys_writel(host->mphy_base, 0x18, 0x2F0);
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ufs_sys_writel(host->mphy_base, 0xC0, 0x120);
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ufs_sys_writel(host->mphy_base, 0xC0, 0x260);
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ufs_sys_writel(host->mphy_base, 0x03, 0x094);
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ufs_sys_writel(host->mphy_base, 0x03, 0x1B4);
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ufs_sys_writel(host->mphy_base, 0x03, 0x2F4);
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ufs_sys_writel(host->mphy_base, 0xC0, 0x08C);
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udelay(1);
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ufs_sys_writel(host->mphy_base, 0x00, 0x08C);
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udelay(200);
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/* start link up */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(MIB_T_DBG_CPORT_TX_ENDIAN, 0), 0x0);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(MIB_T_DBG_CPORT_RX_ENDIAN, 0), 0x0);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(N_DEVICEID, 0), 0x0);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(N_DEVICEID_VALID, 0), 0x1);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(T_PEERDEVICEID, 0), 0x1);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(T_CONNECTIONSTATE, 0), 0x1);
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return 0;
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}
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static int ufs_rockchip_common_init(struct ufs_hba *hba)
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{
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struct device *dev = hba->dev;
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struct platform_device *pdev = to_platform_device(dev);
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struct ufs_rockchip_host *host;
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int err = 0;
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host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
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if (!host)
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return -ENOMEM;
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/* system control register for hci */
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host->ufs_sys_ctrl = devm_platform_ioremap_resource_byname(pdev, "hci_grf");
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if (IS_ERR(host->ufs_sys_ctrl)) {
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dev_err(dev, "cannot ioremap for hci system control register\n");
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return PTR_ERR(host->ufs_sys_ctrl);
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}
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/* system control register for mphy */
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host->ufs_phy_ctrl = devm_platform_ioremap_resource_byname(pdev, "mphy_grf");
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if (IS_ERR(host->ufs_phy_ctrl)) {
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dev_err(dev, "cannot ioremap for mphy system control register\n");
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return PTR_ERR(host->ufs_phy_ctrl);
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}
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/* mphy base register */
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host->mphy_base = devm_platform_ioremap_resource_byname(pdev, "mphy");
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if (IS_ERR(host->mphy_base)) {
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dev_err(dev, "cannot ioremap for mphy base register\n");
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return PTR_ERR(host->mphy_base);
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}
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host->rst = devm_reset_control_array_get_exclusive(dev);
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if (IS_ERR(host->rst)) {
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dev_err(dev, "failed to get reset control\n");
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return PTR_ERR(host->rst);
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}
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reset_control_assert(host->rst);
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udelay(1);
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reset_control_deassert(host->rst);
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host->ref_out_clk = devm_clk_get(dev, "ref_out");
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if (IS_ERR(host->ref_out_clk)) {
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dev_err(dev, "ciu-drive not available\n");
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return PTR_ERR(host->ref_out_clk);
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}
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err = clk_prepare_enable(host->ref_out_clk);
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if (err) {
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dev_err(dev, "failed to enable ref out clock %d\n", err);
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return err;
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}
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host->rst_gpio = devm_gpiod_get(&pdev->dev, "reset", GPIOD_OUT_LOW);
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if (IS_ERR(host->rst_gpio)) {
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dev_err(&pdev->dev, "invalid reset-gpios property in node\n");
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err = PTR_ERR(host->rst_gpio);
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goto out;
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}
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udelay(20);
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gpiod_set_value_cansleep(host->rst_gpio, 1);
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host->clks[0].id = "core";
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host->clks[1].id = "pclk";
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host->clks[2].id = "pclk_mphy";
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err = devm_clk_bulk_get_optional(dev, UFS_MAX_CLKS, host->clks);
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if (err) {
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dev_err(dev, "failed to get clocks %d\n", err);
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goto out;
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}
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err = clk_bulk_prepare_enable(UFS_MAX_CLKS, host->clks);
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if (err) {
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dev_err(dev, "failed to enable clocks %d\n", err);
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goto out;
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}
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if (device_property_read_u32(dev, "ufs-phy-config-mode",
|
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&host->phy_config_mode))
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host->phy_config_mode = 0;
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pm_runtime_set_active(&pdev->dev);
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host->hba = hba;
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ufs_rockchip_set_pm_lvl(hba);
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ufshcd_set_variant(hba, host);
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return 0;
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out:
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clk_disable_unprepare(host->ref_out_clk);
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return err;
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}
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static int ufs_rockchip_rk3576_init(struct ufs_hba *hba)
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{
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int ret = 0;
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struct device *dev = hba->dev;
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hba->quirks = UFSHCI_QUIRK_BROKEN_HCE | UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING;
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ret = ufs_rockchip_common_init(hba);
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if (ret) {
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dev_err(dev, "ufs common init fail\n");
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return ret;
|
||||
}
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||||
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return 0;
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}
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static const struct ufs_hba_variant_ops ufs_hba_rk3576_vops = {
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.name = "rk3576",
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.init = ufs_rockchip_rk3576_init,
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.hce_enable_notify = ufs_rockchip_hce_enable_notify,
|
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.phy_initialization = ufs_rockchip_rk3576_phy_init,
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.suspend = ufs_rockchip_suspend,
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.resume = ufs_rockchip_resume,
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};
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static const struct of_device_id ufs_rockchip_of_match[] = {
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{ .compatible = "rockchip,rk3576-ufs", .data = &ufs_hba_rk3576_vops},
|
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{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, ufs_rockchip_of_match);
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||||
|
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static int ufs_rockchip_probe(struct platform_device *pdev)
|
||||
{
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||||
int err;
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struct device *dev = &pdev->dev;
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const struct ufs_hba_variant_ops *vops;
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vops = device_get_match_data(dev);
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err = ufshcd_pltfrm_init(pdev, vops);
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if (err)
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dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", err);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int ufs_rockchip_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct ufs_hba *hba = platform_get_drvdata(pdev);
|
||||
|
||||
ufshcd_remove(hba);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops ufs_rockchip_pm_ops = {
|
||||
SET_SYSTEM_SLEEP_PM_OPS(ufshcd_system_suspend, ufshcd_system_resume)
|
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SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL)
|
||||
.prepare = ufshcd_suspend_prepare,
|
||||
.complete = ufshcd_resume_complete,
|
||||
};
|
||||
|
||||
static struct platform_driver ufs_rockchip_pltform = {
|
||||
.probe = ufs_rockchip_probe,
|
||||
.remove = ufs_rockchip_remove,
|
||||
.shutdown = ufshcd_pltfrm_shutdown,
|
||||
.driver = {
|
||||
.name = "ufshcd-rockchip",
|
||||
.pm = &ufs_rockchip_pm_ops,
|
||||
.of_match_table = of_match_ptr(ufs_rockchip_of_match),
|
||||
},
|
||||
};
|
||||
module_platform_driver(ufs_rockchip_pltform);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_DESCRIPTION("Rockchip UFS Host Driver");
|
||||
50
drivers/ufs/host/ufs-rockchip.h
Normal file
50
drivers/ufs/host/ufs-rockchip.h
Normal file
@@ -0,0 +1,50 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Rockchip UFS Host Controller driver
|
||||
*
|
||||
* Copyright (C) 2024 Rockchip Electronics Co.Ltd.
|
||||
*/
|
||||
|
||||
#ifndef _UFS_ROCKCHIP_H_
|
||||
#define _UFS_ROCKCHIP_H_
|
||||
|
||||
#define UFS_MAX_CLKS 3
|
||||
|
||||
#define SEL_TX_LANE0 0x0
|
||||
#define SEL_TX_LANE1 0x1
|
||||
#define SEL_TX_LANE2 0x2
|
||||
#define SEL_TX_LANE3 0x3
|
||||
#define SEL_RX_LANE0 0x4
|
||||
#define SEL_RX_LANE1 0x5
|
||||
#define SEL_RX_LANE2 0x6
|
||||
#define SEL_RX_LANE3 0x7
|
||||
|
||||
#define MIB_T_DBG_CPORT_TX_ENDIAN 0xc022
|
||||
#define MIB_T_DBG_CPORT_RX_ENDIAN 0xc023
|
||||
|
||||
struct ufs_rockchip_host {
|
||||
struct ufs_hba *hba;
|
||||
void __iomem *ufs_phy_ctrl;
|
||||
void __iomem *ufs_sys_ctrl;
|
||||
void __iomem *mphy_base;
|
||||
struct gpio_desc *rst_gpio;
|
||||
struct reset_control *rst;
|
||||
struct clk *ref_out_clk;
|
||||
struct clk_bulk_data clks[UFS_MAX_CLKS];
|
||||
uint64_t caps;
|
||||
uint32_t phy_config_mode;
|
||||
bool in_suspend;
|
||||
};
|
||||
|
||||
#define ufs_sys_writel(base, val, reg) \
|
||||
writel((val), (base) + (reg))
|
||||
#define ufs_sys_readl(base, reg) readl((base) + (reg))
|
||||
#define ufs_sys_set_bits(base, mask, reg) \
|
||||
ufs_sys_writel( \
|
||||
(base), ((mask) | (ufs_sys_readl((base), (reg)))), (reg))
|
||||
#define ufs_sys_ctrl_clr_bits(base, mask, reg) \
|
||||
ufs_sys_writel((base), \
|
||||
((~(mask)) & (ufs_sys_readl((base), (reg)))), \
|
||||
(reg))
|
||||
|
||||
#endif /* _UFS_ROCKCHIP_H_ */
|
||||
Reference in New Issue
Block a user